JPH0252885B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a C-MOS amplifier.

Conventionally, a C-MOS amplifier in which C-MOS inverters are connected in cascade as shown in FIG. 1 has been used in many fields. This example has 4 stages connected, P channel MOS-FETs 1 to 4, N channel MOS-FETs 1 to 4,
It consists of FETs 5 to 8 and a feedback resistor 9.
P-channel MOS-FETs 1 to 4 and N-channel MOS-FETs 5 to 8 each constitute a C-MOS inverter, and an input signal is supplied to the first stage terminal Pi, and is sequentially amplified by each stage. An output signal is generated from the fourth stage terminal Po. Generally, C-MOS inverters have an amplification function in a frequency range below a certain frequency, and by cascading them, a much larger amplification factor can be obtained than a single-stage C-MOS inverter. However, the amplification factor in the high frequency region is almost inversely proportional to the frequency, and the upper limit of the operating frequency is naturally determined.

Conventionally, each C-MOS inverter was formed with the same dimensions, and the maximum operating frequency could not be set very high.Therefore, there was a strong desire to increase the maximum operating frequency and improve the amplification factor in the high frequency region.

Therefore, the present invention aims to improve the amplification factor in the high frequency region by sequentially reducing the area of the cascade-connected C-MOS inverters toward the later stages.

First, in order to demonstrate the principle of the present invention, the frequency characteristics of the amplification factor of the C-MOS inverter will be described.

The amplification factor of the C-MOS inverter in the low frequency region is approximately constant regardless of the frequency, and is approximated by the following equation (1).

A (g _nP + g _nN )/(1/rdsP+1/rdeN)
...(1) However, A: Amplification factor of C-MOS inverter g _nP : Mutual conductance of P-channel MOS-FET g _nN : Mutual conductance of N-channel MOS-FET rdsP: Mutual conductance of P-channel MOS-FET in the saturation region Drain resistance rdsN: Drain resistance of the N-channel MOS-FET in the saturation region.

Further, the amplification factor of the C-MOS inverter in the high frequency region is approximately inversely proportional to the frequency, and is approximated by the following equation (2).

A (g _nP + g _nN )/2πf (C _L + C _D )...(2) where f: Frequency C _L : Load capacitance of the C-MOS inverter C _D : Drain capacitance of the C-MOS inverter itself.

Furthermore, the transconductances g _nN , g _nP and
CD is P channel MOS-FET and N channel
When the channel lengths L of MOS-FETs are assumed to be equal, it is expressed by the following equation.

g _nP = μ _P・C _OX・W _P/L・F _P (V _DD , V _TP ) = K ₁・W _P/L ……(3) g _nN = μ _N・C _OX・W _N/L・F _N (V _DD , V _TN ) =K ₂・W _N/L ……(4) C _D K ₃・C _JP・W _P +K ₄・C _JN・W _N ……(5) However, μ _P : Mobility of P channel MOS-FET μ _N : Mobility of N channel MOS-FET W _P : Channel width of P channel MOS-FET W _N : Channel width of N channel MOS-FET L: P, N channel MOS-FET Channel length C _OX : Gate capacitance per unit area F _P (V _DD , V _TP ): Function of V _DD , V _TP F _N (V _DD , V _TN ): Function of V _DD , V _TN V _TP : P Threshold voltage of channel MOS-FET V _TN : Threshold voltage of N-channel MOS-FET K ₁ to _{K 4} : Constant independent of W _P and W _N C _JP : Unit area of drain of P-channel MOS-FET Junction capacitance per unit C _JN : Junction capacitance per unit area of the drain of an N-channel MOS-FET.

Here, if the ratio of the channel widths W _P and W _N is fixed as a constant value r, r=W _P /W _N , so C _D /(g _np + g _np )L・(K ₃・C _JP・W _P +K ₄・C _JN・W _N )
/(K ₁ W _P +K ₂ W _N ) L・(K ₃・C _JP・r+K ₄・C _JN )/(K ₁ r+K ₂ )=K ₅
...(6) becomes.

However, K ₅ is a constant independent of W _P and W _N.

From the above equation (6), it can be seen that CD/(g _np +g _nN ) does not depend on the sizes of W _P and W _N of the C-MOS inverter.

Also, C _L is the load capacitance of the C-MOS inverter, and for the C-MOS inverter located in the middle of the cascade connection, the P of the next stage C-MOS inverter is
Channel MOS-FET and N-channel MOS
-Almost equal to the FET gate capacitance. in fact,
Stray capacitance such as metal wiring capacitance is also included in C _L , but it is negligible compared to the gate capacitance. Therefore, C _L can be approximately approximated by the following equation.

C _L K ₆・C _OX・L(W _P ′+W _N ′)K ₇
(W _P ′+W _N ′)……(7) However, W _P ′; Channel width of the next stage P-channel MOS-FET W _N ′; Channel width of the next stage N-channel MOS-FET K ₆ , K ₇ ; It is a constant that does not depend on W _P ′ and W _N ′.

Also in the next stage C-MOS inverter, if the ratio of channel widths W _P ′ and W _N ′ is a constant value r′, r=W _P ′/W _N ′, so C _L /(g _np + g _nN ) K ₇ (W _P ′+W _N ′)/(K ₁ W _P +K ₂ W _N ) K ₇ (r+1)/(K ₁・r+K ₂ )・W _N ′/W _N K ₈・W _N ′/ W _N ...(8) However, K ₈ is a constant that does not depend on W _N , W _N ′, W _P , and W _P ′.

Therefore, the amplification factor A of the C-MOS inverter in the high frequency region is expressed by the following equation.

A1/2πf・[K ₈ (W _N ′/W _N )+K ₅ ] ...(9) From this equation, it can be seen that the smaller the value of W _N ′/W _N , the larger the value of A tends to be. Recognize. That is, the amplification factor is increased by making the channel width of the FET in the next stage of the cascade-connected C-MOS inverters smaller than that in the previous stage.

Figure 2 is for explaining the results mentioned above, and the horizontal axis shows the logarithm of the frequency f, and the vertical axis shows the amplification factor A.
The logarithm of is taken. Assuming that the line consisting of a and b represents the frequency dependence of the amplification factor per stage of a conventional C-MOS amplifier formed by cascading C-MOS inverters of the same size, the MOS- When the channel width of the FET is reduced, the amplification factor per stage becomes as shown by the broken line b' in the high frequency region, and when compared at the same frequency, the amplification factor improves. Also, the frequency at which the logarithm of the amplification factor becomes 0 is also C
to C', that is, the maximum operating frequency increases.

The present invention applies the above-mentioned principle to a C
- It is applied to a C-MOS amplifier with cascade connection of MOS inverters. For example, if the channel width of the first stage is 1, the channel width of the second stage is 1/2, 3
Reduce the first row to 1/4, the fourth row to 1/8, and so on.

This reduction rate is the area of the entire C-MOS amplifier,
It is necessary to appropriately determine the number of C-MOS inverter stages and the load of the final stage.

As described above, according to the present invention, the cascade-connected C
- Since the dimensions of the MOS inverters are made smaller as they go to the later stages, the amplification factor increases in the high frequency region and the maximum operating frequency increases.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an example of a C-MOS amplifier in which C-MOS inverters are connected in series, and FIG. 2 is a characteristic diagram showing the frequency dependence of the amplification factor. 1~4...P channel MOS-FET, 5~8
...N-channel MOS-FET.

Claims (1)

[Claims] 1. An amplifier is constructed by cascading a plurality of C-MOS inverters made up of MOS-FETs, and the area of each C-MOS inverter is gradually reduced from the front stage to the rear stage. C-MOS amplifier.