JPH025286A - Memory controller - Google Patents

Abstract

PURPOSE:To smooth the reading and writing actions and to improve the data transfer efficiency to shorten the read and write cycle times of a dynamic RAM by means of a page mode and changing the priority in a refresh cycle at the read/write conflict. CONSTITUTION:The refresh request signals produced from a refresh request generating circuit 10 at a fixed interval are accepted by a memory control circuit 9 in the highest priority. The circuit 9 refreshes a dynamic RAM 3 and at the same time switches alternately the priority between the read and write request to hold the priority until the next refresh request is received. At the read/write request conflict, the circuit 9 performs the arbitration based on the priority set at the due time point to fix the priority at the refresh interval and uses a page mode having the high data transfer efficiency. Thus the smooth reading and writing actions are secured and the data transfer efficiency is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method using a DRAM (dynamic RAM).
The present invention relates to a memory control circuit that performs priority arbitration (hereinafter referred to as arbitration) in conflicts between read requests and write requests of a memory circuit.

[Summary of the invention]

The present invention provides a memory circuit using a DRAM in which a memory control circuit switches the priority order of acceptance and execution of read requests and ride requests at regular intervals, and when a read request and a ride request occur simultaneously, or when a read cycle ( If a ride request occurs during a read operation (read operation) and vice versa, a write cycle (
In the event of a conflict (such as when a read request occurs during a write operation), the read request is accepted with priority, the ride request is left waiting, and a read cycle is performed, or the ride request is accepted with priority, and the read request is left waiting. D
The row address is output to the RAM and latched inside the DRAM by the falling edge of the RAS (row address stave) signal. From then on, the CA
By operating the S (column address strobe) signal and changing the column address, continuous read cycle operations and continuous write cycle operations can be performed without changing the RAS signal, and the row address can be set every cycle. DR, where read and write addresses are input during normal cycles, and the access time and cycle time until data output or input is ensured is reduced.
Using the page mode, which is a well-known technology of AM, DRAM
(hereinafter referred to as dynamic RAM) is aimed at increasing data transfer efficiency.

[Conventional technology]

A conventional DRAM memory circuit, for example, is shown in FIG. 2, and includes a memory control circuit 14 and a dynamic RAM 13.
and read data buffer 11 and write data buffer 1
The memory control circuit 14 is configured with arbitration settings in advance by, for example, a microprocessor system (hereinafter referred to as a microcomputer system) not shown, and upon input of a read request signal or a ride request signal, the dynamic RAM 13 receives the RAS signal,
A read cycle that outputs a CAS signal, a WR (write) signal, and an address, and outputs read data from the dynamic RAM 13 to the read buffer 11, and a write cycle that inputs write data from the write buffer 12 to the dynamic RAM 13. When each cycle is completed, the microcomputer system is notified of the completion by a read request signal and a write acknowledge signal, and each request signal is terminated.

In this configuration, the above-mentioned arbitration at the time of conflict between read and write includes (1) a method in which no priority is set between read requests and ride requests, and read cycles and write cycles are fixedly alternated (read cycle A write cycle is always followed by a write cycle, and a read cycle is always provided after a write cycle for a certain period of time regardless of whether the cycle is executed.) (2) A method in which read requests are always given priority (read, (3) A method that always gives priority to ride requests (even if there is a write/read conflict, the read cycle is made to wait for a write cycle). There were three methods: (1) always giving priority to

[Problem to be solved by the invention]

In the read cycle and write cycle of a conventional DRAM circuit, as shown in FIGS. 2, 3, and 4, a row address is input from the memory control circuit 14 to the dynamic RAM 13, and the row address is input by the falling edge of the RAS signal 18. The column address is latched inside the dynamic frame 13, and then the column address is input, and when the CAS signal 19 falls, it is latched internally and the address is determined. And memory control circuit 1
4 outputs the WE scratch signal to the dynamic ram 13,
When the WE damage signal is at a low level, data is written from the write data buffer 12 to the dynamic RAM 13 (during the write cycle shown in FIG. 4), and when the WE scratch signal is at a high level, data is read from the dynamic RAM 13 to the read data buffer 11. (During the read cycle shown in FIG. 3), the RAS and CAS signals 18 and 19, which are both output, both rise to high level, and the process ends. Then, when performing a read or write cycle again, the
As shown in the figure, the RAS and CAS signals 18 of the cycle
．． There is a problem in that it is not possible to lower the RAS signal 18 to a low level and start the next cycle until an RAS precharge T8 time has elapsed after the RAS signal 19 rises. In addition, (1) in the above-mentioned method in which read cycles and write cycles are not prioritized and are fixedly performed alternately, there is a precharge time T and time before and after each cycle, and read and write cycles are performed alternately. Therefore, it is not possible to use the page mode, which reduces the cycle time, and when there is no contention at the same time, when only reading or only writing, there is always an empty cycle after a read cycle or an empty cycle after a write cycle. (2) In the aforementioned patent featuring a read request, when a conflict occurs with the precharge time, the ride request is forced to wait until the end of the read request. After the read cycle ends, a ride request is accepted and a write cycle is started and executed. However, when a read request is input to the memory control circuit 14,
After the write cycle ends, the read cycle is executed again, and the ride request is again made to wait until the read request ends. Therefore, read cycles continue to be executed intensively, and during that time, ride requests may continue to wait, leading to unsmoothed read/write operations and poor data transfer efficiency. (3) In the above-mentioned method that gives priority to read requests, similar to the above-mentioned read request crushing method, the precharge T + time and the continuous There were problems with poor data transfer efficiency caused by executing write cycles and waiting for read requests, and a high-speed and expensive memory circuit.

[Means to solve the problem]

In order to solve the conventional problems, the present invention utilizes a refresh request generation circuit that requests refreshing of the dynamic RAM at regular intervals and a microcomputer system.
Write address and read address are set, and the address counts up; a write row address counter;
Write column address counter, read row address counter, read column address counter, and front 3
An address selector for selecting the output of the own counter group,
The configuration includes a dynamic RAM that reads and writes data, a read buffer and a write buffer that supply data, and a memory control circuit that controls each of these components.

[Effect]

Refresh request signals generated from the refresh request generation circuit at regular intervals are accepted by the memory control circuit with the highest priority. The memory control circuit refreshes the dynamic RAM, alternately switches the priority of read requests and ride requests, and maintains the priority until the next refresh request arrives. When a read request and a ride request conflict, the memory control circuit performs the arbitration according to the priority order at that time, and since the priority +1i 1st place at this refresh interval remains unchanged, the To use the mode, count up the addresses in the write row address counter, write column address counter, read row address counter, and read column address counter.
an address selector that selectively supplies the output of the counter group (write row address counter, write column address counter, read row address counter, read column address counter) to the dynamic RAM as an address, and supplies data to the dynamic RAM. Alternatively, it controls the select signals of the write buffer and read buffer to be taken out, and the RAS signal, CAS signal, and WE flaw signal for reading and writing to the dynamic RAM. Therefore, by switching the priorities using this periodic refresh request signal, the above-mentioned page mode, which allows write cycles similar to continuous read cycles even in the event of contention, can smooth out read and write operations and prevent slippage, improving data transfer efficiency. climb. Also, as a matter of course, if there are no read requests and only ride requests during the read priority period, this means that read priority is given during that period, and no read requests have occurred. Lyknis I.
is accepted by the memory control circuit, and a write cycle is executed. The same applies when the read and write positions are reversed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. 5 and 6 are timing diagrams of an example. A refresh request signal indicating a refresh request is inputted to the memory control circuit 9 at regular intervals from the refresh request generation circuit 10. A fifth refresh acknowledge signal indicating that the refresh cycle has ended is sent to the generating circuit 10.
A write row address count UP signal and a write column address count UP signal are output at the timing of ■ in FIG. Similarly, the read row address counter 7 and the read column address counter 8, to which the read start address is set in advance, are output with the read row address counter I-UP signal and the read column address counter 8, respectively. The UP signal is output respectively, and the 4 write row address, write column address, read row address, and read column address are output from the above address counter groups (write row address counter, write column address counter, read row address counter, read column address counter). Outputs a read select signal and a write select signal that control the input address selector 4, the write data buffer 2 that inputs write data to the dynamic RAM 3, and the read data buffer 1 that outputs read data from the dynamic RAM 3, respectively; It outputs a RAS signal, a CAS signal, and a WR signal for reading and writing data at the address input from the address selector 4 to the dynamic RAM 3. Fifth
As shown in the figure, when the memory control circuit 9 is in the write priority state, when the above conflict occurs due to the generation of the read request signal and the ride request signal, the memory control circuit 9
Since the arbitration is performed and it is a write priority period, a read request signal and a waiting ride request signal are accepted, and a write cycle in the page mode is started.

First, the memory control circuit 9 outputs a write select signal to the address selector 4 in order to give a write row address to the dynamic RAM 3, and also outputs a RAS signal to the dynamic RAM 3 at the timing (3). When the write row address is fetched, the address selector 4 is then used to give the write column address.
and the write select signal to the write data buffer 2, and the WE double signal and the CAS signal to the dynamic RAM 3.
The memory control circuit 9 outputs the write data at the timings of and (3) and captures the write data into the dynamic RAM 3. Thereafter, it starts up at the timing of the EAS signal and the WE double signal (2) to complete the initial write cycle. In order to perform the mode, the output of the RAS signal is held, the write column address counter 6 is set to URL by the write column address count UP signal, and the write column address counted by tJP is sent to the dynamic RAM 3 and write buffer 2 by the write select signal. In addition, the WE double signal - CAS signal is sent to the dynamic ram 3.
By outputting at the timing of write buffer 3
The write data output from the dynamic RAM 3 is taken in, and then raised at the timing of the CAS signal and the WE double signal (■). In this way, while holding the RAS signal and the write row address, the write column address counter 6
As long as the ride request is held, the refresh generation circuit 10 repeatedly updates the write column address by increasing the count of , and executes the page mode write cycle by the CAS signal and WE double signal operation until the refresh cycle in which the priority is switched. When a refresh request signal is input to the memory control circuit 9, the refresh request is accepted at the IT destination, and after page mode dry 1 to cycle completion, the dynamic ram 3 is sent in the order of CAS signal and RAS signal at the timing of ■ and [phase]. At the same time, the read and write priorities are switched, and after the refresh cycle is completed, a refresh acknowledge signal is output to the refresh request generation circuit 10 at the timing (3). Therefore, as shown in FIG. 5, after the refresh cycle ends, the read cycle takes priority, and even if a ride request is input to the memory control circuit 9, if a read request is input, the ride request is given priority. The read request is accepted immediately, and the memory control circuit 9 starts a page read cycle similar to the page write cycle described above. First, the memory control circuit 9 outputs a read on/off signal to the address selector 4 in order to transmit a read row address to the dynamic RAM 3, and also outputs a RAS signal to the dynamic RAM 3 at a timing of 0. When the read row address is fetched into the RAM 3, the read data buffer 1 is sent to the address selector 4 in order to obtain the next read column address, and the read data is output. 3, output the CAS signal and the WE double signal (WE double signal high level) at the timing ■, output the read data to the read buffer 1, then raise the CAS signal at the timing ■ and execute the initial read cycle. 6 Next, in order to perform the page mode, the memory control circuit 9 performs the following steps.
Continuing to hold the output of the RAS signal, give the read column address counter 8 to URL by the read column address count UP signal, give the counted up address to the dynamic RAM 3 and read buffer 1 by the read select signal, and then send the CAS to the dynamic RAM 3. By outputting the signal at the timing of the WE double signal [phase], read data is read from the dynamic ram 3,
It is output to the read buffer 1, and then the CAS signal is raised at the timing of (2). In this way, while holding the RAS signal and the read row address, the read column address, the CAS signal, and the read cycle in the page mode by the WE double signal operation are executed by the call l-UP of the read column address counter 8. As long as the priority is maintained, the process is repeated until the refresh cycle when the priority is changed. Also, as shown in Figure 6, during the write priority period, the read request is made to wait and a page mode write cycle is executed, and the priority is changed according to the refresh cycle. is switched, read priority is given, and a page mode read cycle is executed. At this time, the ride request is kept waiting, but if the page mode read cycle ends during the read priority period (the read request ends at the timing of I9), of course no read request has occurred, so the read priority period Even if there is a read request, the write request is accepted at the timing (3), and unless a read request is input to the memory control circuit 9 during this period, the page mode write cycle is executed until the refresh cycle.

〔Effect of the invention〕

As described above, according to the present invention, read and write access times and cycle times are reduced. Dynamic RAM read cycle using basic mode,
By shortening the write cycle time and switching priorities during read and write conflicts using refresh cycles performed at regular intervals, read and write operations can be smoothed and the data transfer efficiency of the dynamic RAM can be increased.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a DRAM circuit diagram of the present invention, FIG. 2 is a conventional DRAM circuit diagram, FIG. 3 is a dynamic RAM read cycle timing diagram, and FIG. Dynamic RAM write cycle timing diagram. Figure 5 is a timing diagram of priority switching when read and write conflicts occur. Figure 6 is a timing diagram of priority switching when read is given priority.
Timing diagram when a write cycle is accepted. 1 ・ 2 ・ 3 ・ 4 ・ 5 ・ 6 ・ 7 ・ 8 ・ 9 ・ ・Read data buffer ・Write data buffer ・Dynamic ram ・Address selector ・Write row address counter ・Write column address counter ・Read row address counter ・Read column Address counter/memory control circuit refresh refresh read data buffer write data buffer dynamic ram memory control circuit to generate circuit Applicant Seiko Electronics Co., Ltd. Agent Patent attorney Keiyuki Hayashi Suke Data 1 node Q T1; Merge “Takekaku Rei Eve Laflam Reed Cycle Fimin 7” Figure 3 T1
Mi v71 mu right goiful fuimiso 7° diagram Figure 4

Claims (1)

[Claims] A memory circuit using a dynamic RAM, an address selection circuit that provides an address to the memory circuit, a counter circuit that provides an address to the address selection circuit, a data buffer circuit that supplies data to the memory circuit, and the memory circuit. , a memory control circuit that controls an address selection circuit, a counter circuit, and a data buffer circuit; and a refresh generation circuit that requests the memory control circuit to refresh the memory circuit.