JPH0244859A - Picture transmission equipment - Google Patents

Abstract

PURPOSE:To reduce information to be transmitted actually by preventing the information to show the decided result of a deciding means from being transmitted by using selection at a previous picture when the selection of an encoding means is the same. CONSTITUTION:A direction signal to be outputted from the decision circuit 22 controls the switching of a selector switch 34 through a timing control circuit 48. Namely, the selector switch 34 selects data in the direction of a smaller maximum difference among the h(<2k)-bits outputs of vector quantizers 28, 32. The vector quantizer 28 outputs codes q1,1, q1,2, q1,3, q1,4 in turn according to the inputs of DELTA3,1, DELTA2,2, DELTA2,3, DELTA2,4. On the other hand, the quantizer 32 forms similarly the codes q1,1, q1,3, q2,1, q2,3 when DELTA1,2, DELTA1,4, DELTA2,2, DELTA2,4 are inputted, and the output order of them is made to be the order of each small block as q1,1, q2,1, q1,3, q2,2, and the quantizers 28, 32 are regulated so that their timings to output the code q1,1 coincide with each other. Thus, the information to be transmitted actually is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image transmission device, and more specifically, to a device that encodes and transmits image information with high efficiency.

[Conventional technology]

Conventional systems that encode and transmit image data obtained by sampling television signals with high efficiency divide all the pixels that make up the screen into pixel blocks each consisting of multiple pixels, and each pixel block A method is known that performs high-efficiency encoding on a unit-by-unit basis. In pixel block units,
For example, a method of transmitting a pair of data regarding the maximum and minimum values of all pixel values, and a pair of data obtained by quantizing each pixel value based on the maximum and minimum values, within each pixel block. A known method is to transmit pixel data that has been vector quantized all at once in a dimensional space consisting of 100 pixel samples included in the 100% pixel sample.

[Problem to be solved by the invention]

However, in this conventional example, when an image is divided into pixel blocks, the positions of the blocks and the number of pixels in each block are determined in advance, so it is difficult to respond to changes in the image. Furthermore, in the method of vector quantization, if there is a part where the luminance changes sharply, this change cannot be reproduced, resulting in an image with blurred outlines. Therefore,
Not suitable for high-quality image transmission.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image transmission device that can respond to changes in images and has high image reproduction ability.

[Means to solve the problem]

An image transmission device according to the present invention is an image transmission device that divides all pixels constituting an image into blocks each consisting of a plurality of pixels, encodes and transmits one or more blocks as a transmission unit, and a small block forming means that divides the block into a plurality of small blocks;
and a second encoding means, a determining means for determining the direction in which the difference or amount of change between pixel values is smaller in the two directions, and a first and second encoding means according to the determination result of the determining means. selection means for selecting the output of the encoding means, and when the selection of the first and second encoding means differs between screens for at least one small block in the block, the selection data by the selection means is provided. At the same time, information indicating the determination result of the determination means is transmitted, and the first and second
If the selection of the encoding means is the same, the information indicating the determination result of the determination means is not transmitted.

[Effect]

Since the outputs of the first and second encoding means are selected according to the judgment result of the judgment means, highly efficient codes can be obtained in accordance with changes in the image. If the selection of the above encoding means is the same between screens, the selection on the previous = 3 screen can be used, so information indicating the judgment result of the above judgment means is not transmitted. It can be reduced even more.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

Generally, television signals have strong correlation between frames.

That is, a scene in which a scene changes takes a short time compared to the entire time of the broadcast program, and the proportion of pixels that change within one screen is often small compared to the entire screen. Therefore, from an overall perspective, there is no need to attach change information to all pixels and pixel groups, and the amount of transmitted data can be reduced. The present invention focuses on this point.

FIG. 1 shows a block diagram of an embodiment of the present invention. 1
0 is an input terminal for n-bit digital image data (that is, 2' gradation digital image data), and the input data is a raster signal such as a television signal, etc.
It is formed by sampling a scanned analog image signal at a predetermined frequency and linearly quantizing it. The pixel blocking circuit 12 converts the image data at the input terminal 10 into a second
As shown in the figure, the data is divided into blocks and output in pixel blocks each consisting of a pixels in the vertical direction and b pixels in the horizontal direction. That is, one pixel block includes aXb pixels. In the following description, as shown in FIG. 3, the pixel data of each pixel block is generally expressed as Di,j (where i=l to as3=1 to b).

Pixel data in units of pixel blocks output from the pixel blocking circuit 12 is applied to a maximum value detection circuit 14, a minimum value detection circuit 16, and a blocking circuit 18. The maximum value detection circuit 14 detects the maximum value D□ of all pixel data for each pixel block, and the minimum value detection circuit 16 detects the minimum value D sin. The blocking circuit 18
As shown in the figure, one pixel block is
The pixel data is divided into small blocks each including y pixels in the horizontal direction, and pixel data is output in a predetermined order in units of small blocks.

The timing adjustment circuit 20 is a circuit that adjusts the detection work time of the maximum value detection circuit 14 and the minimum value detection circuit 16, and delays the output of the blocking circuit 18 by a time corresponding to the detection work time. Timing adjustment circuit 2
The pixel data time-adjusted at 0 is applied to the division value conversion circuit 21 and the judgment circuit 22. For example, for each pixel block, D ,, l+ D 2+ ++'-1・, D
X, 1. D I+ 2+'-'l D X, y
, --, D81. are applied in this order. The maximum value DmaX and the minimum value 6.7 detected by the detection circuit 14.16 are also applied to the division value conversion circuit 21. The division value conversion circuit 21 compares each pixel data D i + j with the quantization level obtained by dividing the maximum value D-8 and the minimum value D-8 and 8 and 7 into 26, and obtains a k-bit division code Δ.

(Δ1,1 to Δ8.b) is output.

The output of the division value conversion circuit 21 is further vector quantized.

That is, the output of the division conversion circuit 21 is 1 line (IH),
That is, the signal is applied directly to the vector quantizer 28 via the delay circuit 26 for three pixels, and vector quantized between the pixels arranged in the vertical direction. The output of the division value conversion circuit 21 is also directly applied to a vector quantizer 32 via a one-pixel delay circuit 30 and vector quantized between horizontally aligned pixels. The vector quantizer 28 is Δi+j
The vector quantizer 32 operates only when i is an even number.
It only works when is an even number. Further, it is assumed that both ab and ab are even numbers. Further, the vector quantizer 32 is configured to change the output order with respect to the input order so as to output quantization codes in units of small blocks, which will be described later.

On the other hand, in vector quantization by the vector quantizer 2832, the judgment circuit 22 calculates the difference between paired pixels in the vertical and horizontal directions within a small block, and calculates the maximum difference in the horizontal direction and the maximum difference in the vertical direction. Calculate the difference and determine in which direction, horizontal or vertical, the maximum difference occurs. FIG. 5 shows an example of a circuit configuration when a small block consists of 2×2 pixels. 50 is an input terminal, 51.52.53 is 1
8 minute delay circuit, 54.55.56 is 1 pixel delay circuit, 57, 58, 59, 60, 61.62 is subtractor, 6
3 is a comparison circuit, and 64 is an output terminal for a direction signal indicating the direction of the maximum difference. That is, the comparison circuit 63 calculates D i +
It operates only when both '+j in j are even numbers, and outputs a binary signal indicating the above judgment result for each small block.

The direction signal output from the determination circuit 22 controls switching of the selection switch 34 via the timing control circuit 48. That is, the selection switch 34 selects the vector quantizer 28.3.
Among the 2 h (<2k) bit outputs, the data in the direction of the smaller maximum difference is selected. FIG. 6 shows a=4. An example is shown in which a pixel block of 166 pixels with b=4 is divided into small blocks of 4 pixels, and vector quantization is performed every 2 samples. For example, Δ1,1. Δ2,11Δ5,2. Δ2.
In the case of a small block consisting of 2, the difference between Δ11 and Δ1,2 and Δ! Since either the difference between Δ1.1 and Δ2- or the difference between Δ1,2 and Δ2,2 is larger than the difference between +1 and Δ2,2, the horizontal direction of Δ11 and Δ8,2, ΔII and Δ2.2 It shows that combinations are selected and vector quantized.

Here, the vector quantizer 28 described above is Δ3−9Δ2.2
．． Δ218. According to the input of Δ2, 4, the sign qIn I+
Q l+ Z-ql+ 3+ q l+ 4 are output in order. On the other hand, the quantizer 32 similarly processes Δ1, 2, . Δ1.
4. Δ2.2. When Δ2.4 is input, the sign q1,
1, q1131 Q! , 1. (1213 is formed, but the output order is ql+l+ q2=I, qI+3+ Q
Z+3 and each small block are sequentially arranged, and the timings at which these quantizers 28 and 32 output the code Q+++ are adjusted to coincide.

As a result, a vector quantization code is output for each small block.

The above selection information is necessary for reception or image reproduction, so as described later, parallel/serial (P
/S) is sent out to the transmission line via the converter 36. still,
This direction selection information is stored in 1 bit per small block (
W+, l+wZ, +, -9Win j+'----'l
Wu+V) is sufficient. In the above embodiment, U=V-2.

The direction selection information of the judgment circuit 22 is also applied to the comparison circuit 23, and the comparison circuit 23 compares it with the direction selection data of a small block at the same position on the same screen one frame before, which is stored in the data memory 24. , outputs a 1-bit signal f indicating whether or not there is a change in direction selection in one small block within each block.Data memory 2
The stored data in No. 4 is rewritten in units of small blocks only when there is a change in direction selection. Of course, for the first screen, the direction selection data for all small blocks are stored as they are in the data memory 24.

Division code qt,j of h (<2k) bits output from the selection switch 34 (However, for the output of the vector quantizer 28, i is only 1 and 3, and for the output of the vector quantizer 32, j is 1) .3 only) is applied to the P/S converter 38 and output as serial data at a predetermined timing. In addition, the output D□X of the maximum value detection circuit 14
(n bits) is applied to the P/S converter 40, and the output 1.7 of the minimum value detection circuit 16 is applied to the P/S converter 42. The P/S converter 36 contains vector quantization direction selection information Wi,j (1 bit×1
The number of small blocks within the pixel block) is added to the P/S conversion circuit 35, and the above-mentioned direction selection presence/absence information signal f output from the comparison circuit 23 is applied to the P/S conversion circuit 35.

The outputs of the P/S converters 35, 36, 38, 40, 4217) are sequentially selected by the selection switch 44 and become serial data as shown in FIG. FIG. 7(a) shows a case where there is a change in direction selection for at least one small block with respect to the first frame of image transmission processing or the same block of the previous frame, and FIG. A case in which there is no change in the block is shown.

The serial data from the selection switch 44 is stored in a FIFO (
The data transmission rate is kept constant by the buffer 45 (first-in/first-out), and the synchronization addition circuit 46
supplied to The synchronization addition circuit 46 adds a synchronization signal and outputs it to the output terminal 47.

Addition of the synchronization signal in the synchronization addition circuit 46 may be performed for each pixel block or for each predetermined number of pixel blocks.

An image recording/reproducing system such as a VTR is connected to the output terminal 47, for example.

Note that the operation timing of each of the above circuits is uniformly controlled by a timing control circuit 48.

FIG. 8 shows the configuration of a receiving device corresponding to the transmitting device of FIG. Data encoded with high efficiency by the apparatus shown in FIG. 1 is input to the input terminal 70. 71 is a circuit for detecting the presence or absence of direction selection, and 72 is a circuit for detecting the presence or absence of direction selection, and 72 is a circuit for detecting the presence or absence of direction selection;
This is a synchronization separation circuit that separates the synchronization signal added in Figure). The timing control circuit 73 controls the operation timing of the following circuits according to the synchronization signal from the synchronization separation circuit 72, and controls the switching of the switch 74 according to the direction selection data from the circuit 71. That is, if the received code has a significant change in direction selection, the above-mentioned n-bit D□)1. D@
in, an n-bit vector quantization code qi+j, and direction selection information W i + j during vector quantization, and if there is no change in direction selection, D, , , D
□7 and vector quantization code qi.

, and are divided into. Are these S/P converters? 5,
76.77 into parallel data.

Maximum value data D□8 and minimum value data D7.7 output from the S/P converter 75 are launched into a maximum value latch circuit 78 and a minimum value latch circuit 79, respectively. Also,
The direction selection information @W output from the S/P converter 76 is applied to the combination detection circuit 80, and if there is no change in direction selection, the combination detection circuit 8o detects the one frame previous frame stored in the data memory 81. Direction selection information is read out and applied to an inverse vector quantizer 82 (described later), and if there is a change in direction selection, the corresponding storage location in the data memory 81 is
/P converter 76 as well as updating with direction selection information,
This direction selection information is applied to the inverse vector quantizer 82. The vector quantization code qi+j output from the S/P converter 77 is applied to the inverse vector quantizer 82. The inverse vector quantizer 82 performs inverse vector quantization with reference to the direction selection information from the combination detection circuit 8o, and outputs a division code for each pixel.

The divided value inverse conversion circuit 84 converts the maximum value D max and the minimum value D of the maximum value launch circuit 78 and the minimum value launch circuit 79.
The output of the inverse vector quantizer 82 is decoded with reference to min. Since the output of the divided value inverse conversion circuit 84 is in units of pixel blocks, the scan converter 85 converts the scanning direction into an order corresponding to raster scanning. At the output terminal 86, a normal raster scan image signal is obtained.

FIG. 9 shows a transmission system according to another embodiment of the present invention.

In this embodiment, the presence or absence of direction change information f outputted from the comparison circuit 23 is not transmitted, but the receiving side is informed of the presence or absence of direction change based on the transmission order of D□x+Dmin in the transmitted serial data. In other words, the timing control circuit 48 controls the P/S converter 4 according to the output of the comparison circuit 23.
．． Controls the selection order of 0.42. Other configurations are
This is the same as in FIG. In this embodiment, the amount of transmission can be reduced by one bit per transmission block. The transmitted data is shown in Figure 1O.

FIG. 11 shows a block diagram of the configuration of a receiving device corresponding to FIG. 9. In FIG. 11, the circuit 71 is removed and the maximum value, Th
, X and the minimum value , , 7 are provided. Then, the detection result of the detection circuit 88 is applied to the combination detection circuit 80 and the timing control circuit 73 to control the combination detection circuit 80 and the switch 74. The subsequent processing is the same as in the case of FIG.

〔Effect of the invention〕

As can be easily understood from the above description, according to the present invention, the encoding direction can be selected according to the change in the image, and image data can be transmitted with high quality and efficiency.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an embodiment of the present invention, FIG. 2 is a mode of dividing a pixel block, FIG. 3 is an arrangement of pixel data D i + j in a pixel block, and FIG. 4 is a diagram showing how a pixel block is divided. 5 is a specific example of the judgment circuit 22 shown in FIG. 1, FIG. 6 is an example of selecting the direction of vector quantization, FIG. 7 is an example of serialization of transmission data, and FIG.
The figure is a block diagram of the configuration of the receiving device corresponding to FIG.
10 is a configuration block diagram of a transmitting device according to a modified embodiment, FIG. 10 is an example of serial data arrangement according to FIG. 9, and FIG. 11 is a configuration block diagram of a receiving device corresponding to FIG. 9.

Claims (1)

[Claims] An image transmission device that divides all pixels constituting an image into blocks each consisting of a plurality of pixels, encodes and transmits one or more blocks as a transmission unit, and divides the block into a plurality of small blocks. a means for forming small blocks;
First and second encoding means that encode each small block in two directions orthogonal to each other on the screen, and a determination that determines the direction in which the difference or amount of change between pixel values is smaller in the two directions; means and a selection means for selecting the outputs of the first and second encoding means according to the determination result of the determination means, and the first and second encoding means select the outputs of the first and second encoding means between screens for at least one small block within the block. If the selection of the second encoding means is different, information indicating the judgment result of the judgment means is transmitted together with the selection data of the selection means, and the first An image transmission apparatus characterized in that, when the selections of the first and second encoding means are the same, information indicating the judgment result of the judgment means is not transmitted.