JPH0235457B2 - HANDOTAISOCHINOSEIZOHOHO - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a single crystal semiconductor substrate.

In a semiconductor device having a single-crystal semiconductor substrate, especially in a semiconductor integrated circuit having a memory function, even the slightest leakage current can lead to a failure.
For this reason, methods are known that target crystal defects and impurities such as metals in semiconductor substrates. Hereinafter, the conventional Getter method will be explained with reference to FIG.

Note that here we will use MOS based on silicon semiconductors.
Integrated circuits will be explained. In the figure, 1 is a silicon single crystal substrate, 2 and 3 are sources or drains, 4 is a gate insulating film, 5 is a field insulating film, and 6 is an internal metal wiring or a polysilicon layer. 7 is the getter layer. By the way, the getter layer 7 is usually provided on the back surface opposite to the active region, which is the source or drain, and the getter layer 7 can be formed by a method using high concentration diffusion of phosphorus, or by using a getter effect such as phosphorus or argon. A method of implanting certain impurities by ion implantation is known. However, when this method is used, the distance between the getter layer 7 on the back surface and the active region on the front surface is approximately the same as the thickness of the crystal substrate, which is about 200 to 50 microns in the case of a normal silicon semiconductor. Not only does it have the disadvantage of requiring a high temperature or a long time for
In addition, since the getter layer 7 on the back surface is often formed by phosphorus diffusion or ion implantation,
When the getter layer 7 is P-type, the getter layer 7 must be removed in the end to make ohmic contact with the package, which has the disadvantage that the getter effect cannot be fully exerted and the number of steps increases. Furthermore, in order to intentionally mechanically damage the single crystal structure of the getter layer 7 on the back surface to produce a getter effect, a method is known in which the surface of the getter layer 7 is roughened to have irregularities. However, this also has the disadvantage that it not only impairs ohmic contact when adhering to the package, but also that the mechanical adhesion strength is insufficient, resulting in extremely low reliability.
Furthermore, the thickness of a semiconductor substrate increases as the wafer diameter increases, but in order to assemble it into a package, it must be thin to a certain extent and have a constant thickness as much as possible, or it will be difficult to grasp the die, and it will be difficult to connect to external leads. At the same time, large steps can cause problems such as wire breakage and short circuits at the edges of the board.Also, the package size becomes large, which impedes the improvement of the packaging density of the assembled finished product. , it must be thinned in a step near the end of the wafer processing process, and at this time, the getter layer 7 on the back side must be removed, so the getter effect disappears in the subsequent steps, and after this step, the getter layer 7 must be removed. When a getter effect is required, a getter layer must be formed again, which not only increases the number of steps but also has the disadvantage that there are limits to the getter method.

This invention was made in order to eliminate the above-mentioned drawbacks, and it is possible to obtain a getter by implanting impurity ions into the inside of a single crystal semiconductor substrate, that is, deeper than the element formation region and at a predetermined depth from the surface of the semiconductor substrate. The present invention provides a method for manufacturing a semiconductor device that has flexibility in element formation by providing layers and can improve the getter effect without hindering high integration.

An embodiment of a semiconductor device manufactured according to the present invention will be described below with reference to FIG. The active region in FIG. 2 is the same as that in FIG. 1, so the explanation will be omitted.

Figure 2 shows a semiconductor substrate in which an internal getter layer is provided at a predetermined depth from the surface, deeper than the element formation region where the active region of the semiconductor element is formed. The getter layer 10 is provided only at a predetermined depth in the gate region excluding the active region. For example, if a manufacturing method using selective oxidation technology is used to form the getter layer 10 in the source/drain and gate regions, The getter layer 10 of this embodiment can be formed simply by performing ion implantation for the getter before selective oxidation without using a mask just for forming the getter layer 10.

Moreover, in this embodiment, the getter layer shown in FIG. 1 is much closer to the active region consisting of the source and drain than the one on the back side.
Since the heat treatment temperature for the getter is low and the time is short, and since the getter layer 10 is inside the substrate, there are no restrictions on the situation on the back side, ensuring sufficient adhesion and ohmic contact with the package. be able to.

Next, the manufacturing method of the present invention for forming the getter layer 10 shown in FIG. 2 will be described.

First, as shown in FIG. 3, a manufacturing method using selective oxidation technology is used, for example, using a mask 30 with a pattern indicating the source/drain and gate regions.
As shown in FIG. 4, a getter layer 10 is formed by implanting impurities 13 such as phosphorus or argon from the surface of a single crystal semiconductor substrate using ion implantation technology.
form. At this time, the
It is necessary to implant it sufficiently deeper than the source/drain of the MOS transistor. Crystal defects 14 due to the ion implantation occur on the surface side of the getter layer 10 formed at this time.

Next, as shown in FIG. 5, a heat treatment using a laser beam 16 is applied from the surface side of the substrate. This is a so-called laser annealing technique, in which the complete area of the single crystal that remains in the vicinity of the surface of the substrate is used as a seed for annealing. By this laser annealing, the getter layer 10
After the surface side region is annealed to restore single crystallinity, the region near the surface, that is, the device formation region
Forms the source and drain of a MOS transistor. In addition, in the process shown in FIG. 5, if the crystal defect 14 is very large or even a very small crystal defect is problematic in terms of characteristics, even if the crystal defect 14 remains as shown by the broken line in FIG. sauce·
Since it is removed from the drain, there is no practical problem.

In FIG. 5, before laser annealing, epitaxial growth or polycrystalline growth using the same material as the semiconductor substrate is performed. A similar getter layer can also be formed by subsequently performing laser annealing. In addition, this structure can also be used in the SOS (silicon-on-sapphire) structure by providing it near the surface of the silicon single crystal to absorb the strain that occurs at the interface between silicon and sapphire with this getter layer. can.

As described above, the present invention injects impurities such as phosphorus or argon into the source/drain and gate regions of a MOS transistor at a position deeper than the element formation region located on the surface of the substrate and at a predetermined depth below the surface. A highly concentrated impurity layer is formed by implanting ions using a patterned mask, and the surface region is heated and annealed to remove crystal defects in the surface region, after which elements are formed on the substrate. Element formation provides flexibility, improves the getter effect without hindering high integration, and does not cause voltage breakdown defects, lowers the heat treatment temperature for the getter, and reduces the time required for the getter. Not only can it be made shorter, but there are no restrictions on the back surface, which has the effect of ensuring sufficient adhesion and ohmic contact with the package.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to the conventional method, FIG. 2 is a sectional view showing a semiconductor device according to the method of the present invention, and FIGS. It is a sectional view showing a manufacturing process. In the figure, 1 is a silicon single crystal substrate, 2, 3
is the source or drain, 4 is the gate insulating film,
5 is a field insulating film, 6 is an internal metal wiring or polysilicon layer, and 10 is a getter layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Using a semiconductor substrate having a front surface and a back surface,
In this method for manufacturing a semiconductor device in which a source and drain of a MOS transistor are formed in an element formation region up to a predetermined depth from the surface of a semiconductor substrate, before forming the source and drain of the MOS transistor, the element of the semiconductor substrate is An impurity with a getter effect, such as phosphorus or argon, is ionized at a position deeper than the formation region and at a predetermined depth from the surface of the semiconductor substrate using a mask with a pattern indicating the source/drain and gate regions of the MOS transistor. The method is characterized by comprising a step of implanting to form a high concentration impurity layer, and a step of heating and annealing the surface region of the semiconductor substrate in order to remove crystal defects in the surface region of the semiconductor substrate. A method for manufacturing a semiconductor device.