JPH0235336B2 - - Google Patents

Info

Publication number
JPH0235336B2
JPH0235336B2 JP56165349A JP16534981A JPH0235336B2 JP H0235336 B2 JPH0235336 B2 JP H0235336B2 JP 56165349 A JP56165349 A JP 56165349A JP 16534981 A JP16534981 A JP 16534981A JP H0235336 B2 JPH0235336 B2 JP H0235336B2
Authority
JP
Japan
Prior art keywords
address
computer
virtual
absolute
logical address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56165349A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5868285A (ja
Inventor
Shinji Nanba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56165349A priority Critical patent/JPS5868285A/ja
Publication of JPS5868285A publication Critical patent/JPS5868285A/ja
Publication of JPH0235336B2 publication Critical patent/JPH0235336B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56165349A 1981-10-16 1981-10-16 仮想計算機のアドレス変換方式 Granted JPS5868285A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56165349A JPS5868285A (ja) 1981-10-16 1981-10-16 仮想計算機のアドレス変換方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56165349A JPS5868285A (ja) 1981-10-16 1981-10-16 仮想計算機のアドレス変換方式

Publications (2)

Publication Number Publication Date
JPS5868285A JPS5868285A (ja) 1983-04-23
JPH0235336B2 true JPH0235336B2 (enrdf_load_stackoverflow) 1990-08-09

Family

ID=15810663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56165349A Granted JPS5868285A (ja) 1981-10-16 1981-10-16 仮想計算機のアドレス変換方式

Country Status (1)

Country Link
JP (1) JPS5868285A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1213986A (en) * 1983-12-14 1986-11-12 Thomas O. Curlee, Iii Selective guest system purge control

Also Published As

Publication number Publication date
JPS5868285A (ja) 1983-04-23

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