JPH02310762A - Data transmission system, data output circuit, and data input circuit - Google Patents

Abstract

PURPOSE:To reduce the number of output signals that change simultaneously and to prevent the malfunction of a digital circuit by transmitting the signal representing data with either positive polarity or negative polarity with the data to be transmitted. CONSTITUTION:A comparative judging circuit 17, a polarity inversion circuit 18, a polarity signal generation circuit 32, and a selector 19, etc., are provided. The number of change bits of the data desired to output is detected, and it is judged whether or not the number of change bits exceeds the half of the number of all bits, and regular data is outputted when the former is less than the latter, and inverted data is outputted when the former exceeds the latter. By executing such processing at every data to be outputted, the number of change bits that change simultaneously on a bus can be suppressed to the one less than the half of the number of all bits. At a reception side, since it is necessary to recognize the polarity of inputted data, one signal line 26 is added in addition to a signal line for data carrying. In such a way, the power consumption in the digital circuit can be reduced, and also, unrequired electromagnetic wave radiation can be reduced, and the malfunction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a data transmission method suitable for data transmission of parallel data.

[Prior Art] Many information processing devices, from large computers to workstations and personal computers, use CPUs.
The central processing unit, storage device and I/O (I
nputoutput) device. The CPU, storage device, and I10 device are connected by an address bus for transmitting addresses, a data bus for transmitting data, a control bus for transmitting control signals, and the like.

FIG. 6 shows an example of the configuration of a workstation. 1 is a CPU, 2 is a storage device, 3 is a storage control unit, 4 is a memory,
5 is the I10 device, 6 is the CPU address bus, 7 is the CPU
A data bus, 8 a CPU control bus, 9 a memory address bus, 10 a memory data bus, and 11 a memory control bus. In this information processing device,
CPU address bus 6, CPU data bus 7, CPU control bus 8, memory address bus 9. The signals of the memory data bus 10 and memory control bus 11 are 1
The value changes every time the memory is accessed (hereinafter referred to as a bus cycle). For example, 32-bit CP
In the U data bus 7, the voltage values of a maximum of 32 signal lines are “L II to H” or B H11 to I
It changes to I L '1 every bus cycle.

On the other hand, the CPU, storage control unit 3, etc. are implemented using LSI.
It is common to convert it into chips. The problem here is simultaneous switching noise.

That is, when a large number of output terminals in an LSI change simultaneously, the current change in the ground line is large, and the ground line potential inside the LSI changes temporarily due to the inductance component of the ground line. This simultaneous switching noise changes the level characteristics of the input terminal of the LSI, specifically, the voltage range for correctly recognizing "HIf and lLI", causing malfunction. In order to avoid such problems of simultaneous switching noise, it is common in LSIs to limit the number of output terminals that change simultaneously. For example, Hitachi, Ltd.'s gate array LS
In the I and HG28A/E series, the maximum number of output terminals that change simultaneously is 16.

Regarding the number of output terminals that can be changed at the same time of the gate array LSI, please refer to the Hitachi BI-CMOS gate array HG28.
A/E series design manual, AD-0140A
(1986), p. 12.

Conventionally, as a means for reducing the number of output terminals that change simultaneously, a method has been used in which the timing of output changes is dispersed using delay elements. FIG. 7 shows an example of a circuit that delays four signal lines out of eight signal lines that change simultaneously using a delay element and then outputs the delayed signals to the outside of the LSI. 12 is an LSI, 13a to 13d are delay elements, 14a to 14h are output buffers, and 15a to 15h are output terminals. In this example, the four signal output terminals of Do-D3 and the four signal output terminals of D4 to D7 change at different timings, so the maximum number of terminals that change simultaneously among these eight signal output terminals is It can be 4 pieces.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, when there are many signal lines that may change simultaneously, it is necessary to divide them into three or more groups and output them. There is a problem in that the time difference between the signal of the group outputted last and the signal of the group output becomes large.

For example, 32 data bus signals are
If the data is divided into four groups and output, a time difference of as much as 80 ns will occur in the signals within the same data bus.

Furthermore, the power consumption of a digital circuit increases as the signal frequency increases. In integrated circuits made using the CMOS process, internal gate power consumption is low;
Extinguishing a covered sofa that connects a heavily loaded external bus
The power is not small. Therefore, there is a problem in that the power consumption of the information processing device increases as the bus cycle speed increases.

Furthermore, in high-speed circuit elements, the time required to change the output from 11 L 11 to It HII or from P H''' to "L" is short, so the output signal contains high frequency components. However, there is a problem in that unnecessary electromagnetic waves are radiated to the outside of the information processing device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data transmission system that can reduce the number of output signals that change simultaneously and prevent malfunctions of digital circuits.

Another object of the present invention is to provide a data transmission method that can reduce the number of bus signals that change simultaneously even when there is a period in which the bus is in a high impedance state between data transmissions. .

Still another object of the present invention is to provide a data transmission method that can reduce power consumption of an information processing device and reduce unnecessary electromagnetic radiation.

Still another object of the present invention is to provide an integrated circuit (IC) using the above data transfer method.

Still another object of the present invention is to provide an information processing system using the above data transfer method.

[Means for Solving the Problems] In order to achieve the above object, the data transmission method according to the present invention includes a signal indicating whether the polarity of the data is positive logic or negative logic together with the data to be transmitted. It is designed to transmit.

According to another aspect of the data transmission method according to the present invention, the polarity of the data to be transmitted can be changed for each data.

According to another aspect of the data transmission system according to the present invention, when transmitting n-bit parallel data, a 1-bit signal relating to the polarity of the data is added and transmitted.

Further, the data output method according to the present invention is a data output method that outputs parallel data to a bus of multiple bits, and the bits that change when switching one parallel data output on the bus to the next parallel data. The polarity of the parallel data to be output to the bus is determined so that the number is always less than half of the total number of bits. In this case, preferably, a signal related to the determined polarity is output onto the bus together with parallel data thereto.

Another data output method according to the present invention is that when outputting parallel data to a multi-bit bus, all bits of the bus are temporarily set to LL I II after outputting one data and before outputting the next data. The output method is such that the number of bits of the parallel data output on the bus is always more than half of the total number of bits.
The polarity of the parallel data to be output to the bus is determined.

The data input method according to the present invention is a data input method that inputs parallel data from a multi-bit bus, receives a polarity signal regarding the polarity of the parallel data along with parallel data received from the bus, and responds to the polarity signal. Therefore, the polarity of the parallel data is maintained as it is or is inverted.

A data output circuit according to the present invention is a data output circuit that outputs parallel data, and includes a polarity inverting means for inverting the polarity of data to be output, and selecting either data before or after polarity inversion by the polarity inverting means. a selection means, a comparison and determination means for comparing one data to be transmitted and the immediately preceding data and determining whether the number of changing bits is greater than or equal to a predetermined number; and in accordance with the output of the comparison and determination means, The present invention is characterized by comprising a polarity signal creation means for creating a polarity signal for controlling the selection means.

According to another aspect, the data output circuit according to the present invention is a data output circuit that outputs parallel data, and includes a polarity inverting means for inverting the polarity of data to be output, and a A selection means for selecting one of the data is used to compare one data to be transmitted with the output data of the selection means output immediately before, and it is determined whether the number of changed bits exceeds half of the total number of bits. The selection means is controlled in accordance with the comparison and determination means for making the determination and the output of the comparison and determination means.

Another data output circuit according to the present invention is a data output circuit having a plurality of three-state buffers serving as a parallel data output buffer, and detects a case where more than half of all the bits of the parallel data have a constant value. a detection means, a polarity inversion means for inverting the polarity of the parallel data, and depending on a detection signal of the detection means, select either data before or after the polarity inversion of the polarity inversion means and supply it to the three-state buffer. and a three-state buffer that outputs the detection signal of the detection means.

Still another data output circuit according to the present invention divides all bits of parallel data into two sets, separately provides one of the above data output circuits for each set, and provides the above two sets.
For only one of the sets, delay means for delaying the output data is provided after the selection means.

A data input circuit according to the present invention is a data input circuit that receives parallel data and a polarity signal regarding the polarity of the parallel data, and includes a polarity inverting means for inverting the polarity of the input parallel data, and a polarity inverting means for inverting the polarity of the input parallel data, and , and selection means for selecting either data before or after polarity inversion by the polarity inversion means.

Further, the integrated circuit according to the present invention is an integrated circuit that outputs parallel data, and includes a polarity inversion means for inverting the polarity of data to be output, and a selection means for selecting data before and after the polarity inversion by the polarity inversion means. , a comparison and determination means for comparing one data to be transmitted with the immediately preceding data and determining whether or not the number of changed bits is greater than or equal to a predetermined number; and said selection means in accordance with the output of said comparison and determination means. It has polarity signal creation means for creating a polarity signal to be controlled, an output terminal for outputting the parallel data selected by the selection means, and an output terminal for outputting the polarity signal.

Another integrated circuit according to the present invention is an integrated circuit that receives parallel data and a polarity signal regarding the polarity of the parallel data, the integrated circuit comprising: a polarity signal input terminal that receives the polarity signal;
a plurality of data input terminals that receive the parallel data;
The parallel data input to the data input terminal is taken in as is, depending on the polarity signal input to the input terminal.

Alternatively, it is provided with data import means for inverting and importing the data.

An information processing system according to the present invention is an information processing system that transmits data between a plurality of digital devices via a plurality of signal lines. At least one of the plurality of signal lines carrying the digital signal has a polarity conversion means for converting the polarity of the transmission data so that the polarity of the transmission data becomes
The book has a signal line that transmits information regarding the polarity switching, and has polarity conversion means within the digital device that receives the data to convert the polarity of the received data in accordance with the polarity switching information. It is.

In addition, in this specification, "positive logic" means a logic value of "1"
``'' corresponds to the voltage value It HII, and ``
"Negative logic" means that the logic value It OII is converted to the voltage value LL L
11.

[Function] When n-bit parallel data changes from one value to another value, the number of bits that change is i (O≦i≦n)
If so, the number of bits that do not change is (ni). At this time, when the "other value" is inverted, the number of bits that change compared to the "one value" becomes (ni), and the number of bits that do not change becomes i. The present invention focuses on the properties of this digital value, and when the number of changing bits exceeds half of the total number of bits n, the data to be transmitted (or output) is inverted, and the bus (or output signal) is The aim is to always keep the number of simultaneously changing bits on the line) to less than half of the total number of bits.

To do this, on the data output side, the number of changed bits of the data to be output is detected, and it is determined whether this number of changed bits exceeds half of the total number of bits. If it does not exceed half, the original data is If the value is exceeded, the inverted data is output. By executing this process for each piece of data to be output, the number of simultaneously changing bits on the bus can always be suppressed to less than half of the total number of bits.

Therefore, the power consumption of the digital circuit is reduced, unnecessary electromagnetic radiation is reduced, and malfunctions are prevented.

Note that the data receiving side needs to recognize the polarity of the input data, so it receives a signal indicating the polarity of the data (or a signal related to polarity) from the output side and processes the input data according to this signal. Use as is or invert. for that.

In the present invention, in addition to the signal line for data transmission, there is one signal line.
This book will be added.

The present invention is not limited to application between integrated circuits, but can also be widely applied between digital circuits within an integrated circuit or between information processing devices as long as parallel data is transmitted.

(Hereafter, margin) [Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing a data output section of an LSI. 12 is an LSI, 14a to 1, 41 are output buffers, 15a to 15i are output terminals, 16a, 1
6b is a latch circuit, 17 is a comparison judgment circuit that compares two 8-bit data bit by bit and outputs 11 HIt as judgment signal 25 when the number of different bits is equal to or more than It 5 #, 18 is a polarity of 8-bit input data. 32 is a polarity signal generation circuit, and 19 is a selector.

The comparison/judgment circuit 17 compares the 8-bit internal data 20 with the data 24 from one bus cycle before, latched by the latch circuit 16a, and sets the determination signal 25 to 11 Hlj when the number of different bits is 5 or more.

The polarity signal generating circuit 32 inverts the polarity signal 26 to the opposite polarity to the value in the previous bus cycle when the judgment signal 25 is 'H', and inverts the polarity signal 26 when the judgment signal 25 is tl L j). Keep the value from the previous bus cycle.

The polarity signal 26 created in this way is output to the output buffer 1.
4i and is output to the output terminal 15i.

On the other hand, when the polarity signal 26 is L'', the selector 19 selects the internal data 2o, and when the polarity signal 26 is H'', the selector 19 selects polarity inverted data 2o, which is the polarity of the internal data 20 inverted.
Select 1. The selector output 22 is connected to the latch circuit 16 to prevent data from being output in an uncertain state.
After latching once by b, the output buffers 14a to 1
After 4h, the signal is output to output terminals 15a to 15h.

FIG. 2 is an example of a circuit that implements the comparison/judgment circuit 17 of FIG. 1. 27a to 27h are exclusive OR (FOR)
The gate 28a is a decoding circuit. FOR gate 2
Each bit of internal data 20 and data 24 one bus cycle before are input to 7a to 27h, respectively. Each of the FOR gates 27a-27h outputs It HD when the two inputs are different. Therefore, EOR gate 27a~
The number of gates outputting It H++ in 27h is
This is the number of bits that have different values between internal data 2o and data 24 one bus cycle before. The decoding circuit 28a is an EO
When the number of bits of 11H++ of the 8-bit value input from R gates 27a to 27h is 5 bits or more ((H
When the number of bits of It H++ is 4 or less, L 7'' is output as the determination signal 25. The decoding circuit 28a can be easily realized using an AND gate, an OR gate, or a ROM.

FIG. 3 is an example of the polarity signal generation circuit 32 shown in FIG. 33 is a JK flip-flop, and 34 is a clock signal inputted every bus cycle.

When the JK flip-flop 33 receives a clock signal, it inverts the polarity signal 26 when the 1 judgment signal 25 is It H++, and inverts the polarity signal 2 when the judgment signal 25 is tt L n.
6 is kept in the state it was in the previous bus cycle.

The operation of the LSI output section shown in FIG. 1 will be explained in detail with reference to FIG. 9.

Each internal data 20 to be output to output terminals 15a to 15h
are sequentially fetched into the latch circuit 16a according to the clock, and its output is the data 24 one bus cycle before the internal data 20.The six data 2o and 24 are judged by the comparison judgment circuit 17 as to the number of changed bits, and the judgment signal 25 is output. In this example, as mentioned above,
Comparison judgment signal 2 when the number of changed bits is rr 5 u or more
5 becomes "1". Based on this determination signal 25, the JK Friso flip-flop 33 in the polarity signal generation circuit 32
generates a polarity signal 26 in synchronization with its clock input. That is, the JK flip-flop 33 operates to invert the polarity signal 26, which is the Q output, every time the determination signal 25 becomes II I ++. The internal data 20 is
When the number of bits changed to the previous data held in the latch 16b is less than or equal to It 4 I+, the JK flip-flop 33 does not change the polarity so as to maintain the current polarity. The polarity signal 26 controls the switching of the selector 19, and a selector output 22 corresponding to the polarity of the polarity signal 26 is obtained from the selector 19. The selector output 22 is held in the latch 16b in synchronization with its clock input.

This latch output 23 is outputted to output terminals 15a-15h via buffers 14a-14h. On the other hand, the polarity signal 26 is outputted to the output terminal 15i via the buffer 14i.

Table 1 shows an example of data output in this embodiment.

Table 1 Bus cycle Internal data 20 Output data 23
Polarity signal 261 LLLLLLLL LLLL
LLLL L2 HLLLLLLL
HLLLLLLLL L3 HHHHHH
HHLLLLLLLLL H4LLLLHHHH
HHHHLLLL H5HHHHLLLL
HHHHLLLLL Table 2 shows the number of changing signals between bus cycles in the above output example.

Table 2 Bus cycle Internal data 20 Output data 23 Polarity signal 26 In this way, even when many bits of internal data 20 change, the number of bits that change in output data 23, that is, the number of output signals that change simultaneously is 4. It can be as follows. In addition, (when the number of signals in which the output data 23 changes is four, the polarity signal 26 does not change. Therefore, the maximum number of simultaneously changing output signals, which is the sum of the output data 23 and the polarity signal 26, is also 4 or less, which is 1. This can be reduced to less than half of what it would be without the invention.

Note that in the circuit shown in FIG. 1, the output 23 of the latch 16b may be used instead of the output 24 of the latch 16a input to the comparison/judgment circuit 17. In this case, the latch 16a becomes unnecessary, and since the determination signal 25 itself functions as a polarity signal, the polarity signal generation circuit 32 is also unnecessary. However, in order to eliminate signal instability, it is desirable to place another latch circuit at the position of the polarity signal generation circuit 32.

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

12 is an LSI, 18 is a polarity inversion circuit, 19 is a selector,
28b is a decoding circuit, 298-29h are three-state buffers, 15a-15i are output terminals, and 30 is a pull-up resistor. The three-state buffer enable signal 32 becomes "HII" at the time of bus cycle switching.
h becomes a high impedance state, and the external data 35a
~35h and external polarity signal 35i are connected to pull-up resistor 3
o becomes N HII. On the other hand, the decoding circuit 28
b is the polarity signal 2 when 5 or more of the 8 pin signal lines of the internal data bus 20 are LL L II.
6 as 11 L II. Selector 19 is polarity signal 2
When the polarity signal 26 is It HII, the internal data 2o is selected, and when the polarity signal 26 is II L II, the polarity inverted data 21 obtained by inverting the polarity of the internal data 20 is selected. The selector output 22 is a three-state buffer 29a-2.
After 9h, the signal is output to the output terminals 15a to 15h.

Table 3 shows an example of data output in this embodiment.

I HHHHHHHHHHHHHHH (T)
(HHHHHHHHH) (H)2
LLLLHHHHLLLLHHHHHH(T)
(HHHHHHHHH) (H)3
LLLLLLHHHHHHHHLLLL L(T
) (HHHHHHHH) (H
)4 LLLLLLLL HHHHHHHHHL (
T) (HHHHHHHH) (
H)5 LHHHHHHHHHLHHHHHHHH Here, the bus cycle indicated by (T) indicates a state in which the three-state buffers 29a to 29h become high impedance at the time of bus cycle switching.

Table 4 shows the number of changing signals between bus cycles in the above output example.

(The following is a blank space) Table 4 Bus cycle External data 35a to 35h External polarity signal 35i1-(T) O0 (T) -240 2-(T) 4 0
(T)-33, 1 3-(T) 3
1(T) -401 4-(T)'0 1(T)-51
0 In this way, even when many bits of the internal data 20 change, the number of changing bits of the external data 35a to 35h, that is, the number of signals changing simultaneously can be kept to 4 or less. Furthermore, when the number of changing signals of the external data 35a to 35h is four, the external polarity signal 35i does not change.

Therefore, the external data 35a to 35h and the external polarity signal 35
The maximum number of simultaneously changing signals including i is also 4 or less, which can be reduced to less than half of the case where the present invention is not used.

FIG. 5 shows a circuit example of a device for inputting data output by the two embodiments described above. 12 is LSI, 36
a to 36i are input terminals, 37a to 37i are input buffers, 18 is a polarity inversion circuit, and 19 is a selector.

The polarity inversion circuit 18 creates an inverted input data signal 40 by inverting the polarity of the input data signal 39. The selector 19 selects one of the input data signal 39 and the inverted input data signal 4o according to the polarity input signal 38, and selects the internal input data 4o.
Output as 1. The internal input data 41 is input to the LS 11 in the same way as the data input by the conventional data transmission method.
It can be used inside 2.

FIG. 8 is a diagram showing an embodiment in which the present invention is combined with a conventional method for reducing the number of simultaneously changing outputs using delay elements. The feature of this embodiment is that the circuit shown in the first embodiment is
One of the signals is output after passing through a delay element. The 16-bit internal data 20a is divided into two 8-bit internal data 20b and 20c. The polarity when outputting the internal data 20b and 20c to the output terminals 15, 15' is determined in the same manner as in the first embodiment so that the number of signal changes is less than half. Internal data 2
After the polarity of 0b is selected by the selector 19, it passes through the latch circuit 16b and the output buffer 14, and then is output to the output terminal 1.
5 is output. At this time, the polarity signal 26 is simultaneously outputted to the output terminal 15i through the output buffer 14i. On the other hand, after the polarity of the internal data 20c is selected by the selector 19', the latch circuit 16b', the delay element 13f,
It passes through the output buffer 14' and is output to the output terminal 15'. At this time, the polarity signal 26' is simultaneously transmitted to the delay element 13e,
It is output to an output terminal 151' through an output buffer 141'. In this way, the 16-bit internal data 20a that changes simultaneously is output as two sets of 8-bit data with polarity signals with the number of simultaneous changes being 4 or less, and the change timing of the two 8-bit data is controlled by a delay element. Because they are staggered, they do not change at the same time. Therefore, the number of simultaneously changing signals including the two sets of 8-bit data can be set to four at maximum.

In the embodiments described above, examples were shown in which 8-bit and 16-bit data were transmitted, but any number of bits greater than 2 bits may be used. Moreover, it may be used not only for LSI but also for data transmission between other ICs or devices.

[Effects of the Invention] According to the present invention, it is possible to reduce the number of output signal terminals of an LSI that change simultaneously, so there is an effect that malfunction of the LSI due to simultaneous switching noise can be prevented. Furthermore, in the data transmission system of the present invention, the number of signal changes can be reduced, so that the power consumption of the information processing device can be reduced and unnecessary electromagnetic wave radiation can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing details of one block in FIG. 1, and FIGS.
FIG. 5 is a configuration diagram of another embodiment of the present invention, FIG. 6 is an example of the configuration of a workstation, and FIG. 7 is an explanatory diagram of a conventional system.
FIG. 8 is a block diagram of still another embodiment of the present invention, and FIG. 9 is an operation timing diagram of the circuit of FIG. 1. 12...LSI, 14a-14i...output buffer. 15a-151...output terminal, 16a-16b...
Latch circuit, 17... Comparison/judgment circuit, 18... Polarity inversion circuit, 19... Selector, 20... Polarity signal generation circuit.

Claims (1)

[Scope of Claims] 1. A data transmission system characterized by transmitting, together with the data to be transmitted, a signal indicating whether the polarity of the data is positive logic or negative logic. 2. A data transmission method characterized in that the polarity of the data to be transmitted can be changed for each data. 3. A data transmission system characterized in that when transmitting n-bit parallel data, a 1-bit signal relating to the polarity of the data is added and transmitted. 4. A data output method that outputs parallel data to a multiple-bit bus, and when switching from one parallel data output to the above bus to the next parallel data, the number of changing bits is always half of the total number of bits. A data output method characterized in that the polarity of the parallel data to be output to the bus is determined as follows. 5. The data output method according to claim 4, wherein the signal related to the determined polarity is outputted onto the bus together with the next parallel data. 6. When outputting parallel data to a multi-bit bus,
A data output method in which all bits on the bus are temporarily set to "1" after outputting one data and before outputting the next data, the number of bits that become "1" in the parallel data output on the bus. A data output method characterized in that the polarity of parallel data output to the bus is determined so that the number of bits is always more than half of the total number of bits. 7. A data input method that inputs parallel data from a multi-bit bus, in which a polarity signal regarding the polarity of the parallel data is received together with the parallel data received from the bus, and the polarity of the parallel data is determined according to the polarity signal. A data input method characterized by maintaining or inverting the data as it is. 8. A data output circuit for outputting parallel data, comprising: polarity inversion means for inverting the polarity of data to be output; selection means for selecting either data before or after polarity inversion by the polarity inversion means; Comparison and determination means for comparing exponentiation data and immediately preceding data and determining whether the number of changed bits is greater than or equal to a predetermined number; and controlling the selection means in accordance with the output of the comparison and determination means. A data output circuit comprising: polarity signal creation means for creating a polarity signal. 9. A data output circuit for outputting parallel data, comprising: polarity inversion means for inverting the polarity of data to be output; selection means for selecting either data before or after polarity inversion by the polarity inversion means; Comparing and determining means for comparing the exponentiation data and the output data of the selecting means output immediately before, and determining whether or not the number of changing bits exceeds half of the total number of bits; and the output of the comparing and determining means. A data output circuit characterized in that the selection means is controlled according to. 10. In a data output circuit having a plurality of three-state buffers as output buffers for parallel data, a detection means for detecting a case where more than half of all bits of the parallel data have a constant value; polarity inversion means for inverting polarity; selection means for selecting either data before or after the polarity inversion of the polarity inversion means according to a detection signal of the detection means and supplying the selected data to the three-state buffer; and the detection means A data output circuit comprising a three-state buffer that outputs a detection signal. 11. All the bits of the parallel data are divided into two sets, and the data output circuit according to claim 8, 9 or 10 is separately provided for each set, and only one of the two sets is provided at a stage subsequent to the selection means. A data output circuit comprising a delay means for delaying the output data. 12. A data input circuit that receives parallel data and a polarity signal regarding the polarity of the parallel data, comprising: polarity inverting means for inverting the polarity of the input parallel data; 1. A data input circuit comprising: selection means for selecting either data before or after polarity inversion. 13. An integrated circuit that outputs parallel data, comprising: polarity inversion means for inverting the polarity of data to be output; selection means for selecting data before and after polarity inversion by the polarity inversion means; and one data to be transmitted. Comparing and determining means for comparing the data with the immediately preceding data and determining whether the number of changed bits is greater than or equal to a predetermined number; and generating a polarity signal for controlling the selecting means in accordance with the output of the comparing and determining means. An integrated circuit comprising: polarity signal generating means; an output terminal for outputting parallel data selected by the selection means; and an output terminal for outputting the polarity signal. 14. An integrated circuit that receives parallel data and a polarity signal regarding the polarity of the parallel data, the circuit comprising: a polarity signal input terminal that receives the polarity signal; a plurality of data input terminals that receive the parallel data; and an input terminal that receives the parallel data. 1. An integrated circuit comprising: data capture means for capturing the parallel data input to the data input terminal as is or inverting the parallel data in accordance with the polarity signal input to the data input terminal. 15. In an information processing system that transmits data between multiple digital devices via multiple signal lines, the transmitted data is controlled so that the number of simultaneously changing bits of the transmitted data is minimized within the digital device that transmits the data. a signal line for transmitting information regarding the polarity switching as at least one of the plurality of signal lines for carrying the digital signal; An information processing system comprising: polarity conversion means for converting the polarity of the received data according to the information regarding the polarity switching.