JPH02308634A - Bit buffer circuit for data communication equipment - Google Patents

Bit buffer circuit for data communication equipment

Info

Publication number
JPH02308634A
JPH02308634A JP1129519A JP12951989A JPH02308634A JP H02308634 A JPH02308634 A JP H02308634A JP 1129519 A JP1129519 A JP 1129519A JP 12951989 A JP12951989 A JP 12951989A JP H02308634 A JPH02308634 A JP H02308634A
Authority
JP
Japan
Prior art keywords
equipment
clock
circuit
latched
inside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1129519A
Inventor
Takao Matsuda
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1129519A priority Critical patent/JPH02308634A/en
Publication of JPH02308634A publication Critical patent/JPH02308634A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To surely prevent the consecutive error occurrence of a reception data by applying inversion every time the rising timing of an internal clock and that of a transmission clock of an external device approach together.
CONSTITUTION: The transmission data of an external equipment 2 is latched with a clock supplied from the equipment 2 by a latch circuit 10. Moreover, the output of the circuit 10 is latched by a latch circuit 12 with a clock obtained in the inside of a data communication equipment 4. Furthermore, the output of the circuit 12 is latched by a latch circuit 14 by using the clock acquired in the inside of the equipment 4. Then the rising timing of the clock supplied form the external equipment 2 and that of the clock obtained in the inside of the equipment 4 are detected by a detection circuit 16 and the internal clock of the equipment 4 is inverted by an inverting circuit 18 every time both the detection timings are approached.
COPYRIGHT: (C)1990,JPO&Japio
JP1129519A 1989-05-23 1989-05-23 Bit buffer circuit for data communication equipment Pending JPH02308634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1129519A JPH02308634A (en) 1989-05-23 1989-05-23 Bit buffer circuit for data communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1129519A JPH02308634A (en) 1989-05-23 1989-05-23 Bit buffer circuit for data communication equipment

Publications (1)

Publication Number Publication Date
JPH02308634A true JPH02308634A (en) 1990-12-21

Family

ID=15011510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1129519A Pending JPH02308634A (en) 1989-05-23 1989-05-23 Bit buffer circuit for data communication equipment

Country Status (1)

Country Link
JP (1) JPH02308634A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9158310B2 (en) 2011-12-14 2015-10-13 International Business Machines Corporation Integrating a data center thermal control system and individual fan controllers for controlling a thermal environment in a data center room
US9176508B2 (en) 2012-01-09 2015-11-03 International Business Machines Corporation Managing workload distribution among computing systems to optimize heat dissipation by computing systems

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9158310B2 (en) 2011-12-14 2015-10-13 International Business Machines Corporation Integrating a data center thermal control system and individual fan controllers for controlling a thermal environment in a data center room
US9158311B2 (en) 2011-12-14 2015-10-13 International Business Machines Corporation Integrating a data center thermal control system and individual fan controllers for controlling a thermal environment in a data center room
US9176508B2 (en) 2012-01-09 2015-11-03 International Business Machines Corporation Managing workload distribution among computing systems to optimize heat dissipation by computing systems
US9459633B2 (en) 2012-01-09 2016-10-04 International Business Machines Corporation Managing workload distribution among computing systems to optimize heat dissipation by computing systems

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