JPH02306357A - Data processor - Google Patents

Abstract

PURPOSE:To prevent a program size from becoming large by inserting a non- execution state which does not start a bus cycle when an instruction accessing an external device having a recovery time continues. CONSTITUTION:A register 17 gives a signal showing the number of dummy states, which is set from an external part, to a three state buffer 18 through a data bus 16, and the three state buffer 18 transmits the number of the dummy states to a bus control part 15 when a register enable signal RE is in an active state. In the case of accessing the external device having the recovery time, the dummy states are inserted between before and after the bus cycles and the bus cycles are prevented from being started during that time. Thus, the external device can continuously be accessed by satisfying the recovery time without depending on software, and the necessity of adding excessive instructions for satisfying the recovery time is eliminated from being added to a program. Thus, the program size is prevented from becoming large.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that exchanges data with other devices using bus cycles.

[Conventional technology]

A bus cycle is used to exchange data with an external device such as a memory in a data processing device, and determines the amount of time the bus that connects the data processing device and the external device is occupied. .

The bus cycle is an integer multiple of the reference clock, and by activating the bus cycle, buses such as the system bus are controlled in a time division manner, and processes such as memory read and write and I10 port input/output are executed. There is.

In a data processing device that accesses external devices and transfers data using hash cycles, continuous access is made to the external device that requires recovery time, which is the amount of time needed to perform internal processing on the device, between one access and the next access. In this case, a conventional method has been used in which a dummy period of time during which nothing is executed is set using software to satisfy the recovery time.

FIG. 4 is a block diagram showing the configuration of a conventional data processing device using such a method, and FIG. 5 is a block diagram showing a bus cycle operated by the data processing device shown in FIG. Figure 6 is a diagram showing a lotus cycle when a dummy hour is inserted by software. In the data processing device 1) shown in FIG. 4, when an instruction is transferred into the data processing device 1) via the data bus 16, the hash control section 15 starts a bus cycle, and the instruction fetching means 1
Take the command into 2. The fetched command is sent to the command decoding means 13 by a signal from the Hass control section 15, decoded by the command decoding means 13, and then it is determined how to execute it. When the command is determined, the lotus control unit 15
sends the determined command to the command execution means 14, which starts the hash cycle to execute the command, completing the processing of one command.

Next, with reference to FIGS. 4 and 5, a procedure for executing a plurality of instructions that successively access an external device that requires recovery time will be described.

The recovery time q is the same for both the instruction with the instruction capture hash cycle as AI and the instruction execution bus cycle as ^2, and the instruction B with the instruction capture hash cycle as 81 and the instruction execution hash cycle as 82. If the instruction is to access a specified external device, after the execution hash cycle A2 for the instruction ends, the execution hash cycle B2 of the instruction B can be started again after the recovery time q. However, as shown in FIG. 5, when instructions A and B that access an external device whose recovery time q is longer than the bus cycle are consecutive, the execution bus cycle of instruction B starts from the end of the execution bus cycle A2 of instruction A. The time until the start of B2 is only one cycle of the Hass cycle, which is shorter than the recovery time q, so the time q cannot be satisfied. Therefore, in such a case, in order to satisfy the recovery time q, a bus cycle D1 for fetching an instruction by a dummy processing instruction is inserted by software as shown in FIG. 6, and a hash cycle is activated. Here, the instruction is an instruction that does not execute anything, and the hash cycle is not activated in the execution instruction.

[Problem to be solved by the invention]

As shown in ``2'' below, when executing consecutive instructions to an external device that has a recovery time, it is necessary to insert dummy processing instructions by software in order to satisfy the recovery time. Therefore, there was a problem that the size of the program became large.

This invention was made to solve these problems, and when there are consecutive instructions that access an external device with a recovery time, the recovery time is achieved by inserting a non-execution state that does not start a bus cycle. It is an object of the present invention to provide a data processing device that can perform continuous access in a time-satisfactory manner by executing consecutive instructions, prevents enlargement of program size, and can perform all processing using only the necessary execution software. purpose.

[Means to solve the problem]

The data processing device according to the present invention is provided with a signal output means for outputting a signal to an external device having a recovery time to continuously insert a non-execution state that satisfies the recovery time and enables access even in a hash cycle. , the signal is selected by a predetermined selection signal.

[Effect]

In this invention, when the selection signal is in the active state in any bus cycle, the signal output from the signal output means is selected, a non-execution state is inserted after the end of that bus cycle, and the selection signal is in the inactive state. When it is not selected,
No non-executing states are inserted.

Accordingly, when accessing an external device that requires recovery time continuously, the selection signal is kept active and a non-execution state is inserted by hardware in order to satisfy the recovery time.

〔Example〕

Hereinafter, the present invention will be explained in detail based on the drawings showing one embodiment thereof. FIG. 1 is a block diagram showing the configuration of a data processing device according to the present invention. In the data processing device 1), the instruction sent via the data bus 16 is transferred to the instruction fetching means 1 by activation of a hash cycle from the bus control section 15.
Incorporated into 2. The fetched instruction is sent to the instruction decoding means 13 by No. 13 from the bus control section 15, where it is decoded and it is determined how to execute it. When the command is determined, the bus control unit 15 sends the determined command to the command execution means 14, which starts a bus cycle to execute the command, completing the processing of one command.

Further, the 1/register 17, which is a signal output means, outputs a signal indicating the number of dummy states (one hour) that are non-executing states in which the cycle is not activated. Set externally. The register 17 provides a signal indicating the set number of dummy states to the bus control section 15 via a 3-stay 1 buffer 18 which is a selection means.

In the bus control unit 15, the dummy stay 1 of the input signal
A dummy state is inserted between bus cycles based on the number. Further, a register enable signal 17E is given to the 3-state buffer 18, and when the register enable signal RE is active, dummy stay 1/number is selected and sent to the bus control unit 15, and a dummy state is inserted between bus cycles. be done.

Next, the operation of the data processing apparatus of the present invention configured as described above will be explained. FIG. 2 is a hash cycle diagram showing the operation of the data processing device.

When there is an instruction to access an external device outside the data processing device 1), the instruction to be executed is first imported into the instruction importing means 12, and the instruction decoding means 13 determines whether the instruction should be executed in the following manner. 1 by executing the instruction in the instruction execution means 14 in the next bus cycle.
Processing of one instruction is completed. The command importing means 12, the command decoding means 13, and the command execution means 14 all propagate commands and perform operational processing under the control of the hash control section 15. Further, if there is an instruction to access an external device, the access to the external device is performed at the execution stage of the instruction. That is, access to the external device is performed by activation of the execution bus cycle by the bus control unit 15.

Now, in the same way as described above, the instruction whose fetch bus cycle is At and the instruction execution bus cycle is Δ2 is transferred to the instruction whose fetch bus cycle of the instruction is old and the instruction execution bus cycle is B2. Consider the case where both commands B and B are instructions for accessing an external device for which a recovery time q is specified. The number of dummy states (time) is set in advance for j/register 17 so that access to the external device is first performed in path nicle A2, and then the next execution bus cycle B2 is activated after recovery time q1 of the external device. Set RL. That is, the number r of dummy states is set to be longer than the difference between the recovery time q and the time of the instruction B capture bus cycle B1. Furthermore, by setting the register enable signal RE to be active only when accessing an external device,
External devices can be accessed continuously by successive commands.

FIG. 3 is a bus cycle diagram when an external device is accessed multiple times with one command. Instruction C has an instruction capture bus cycle of 01, an instruction execution bus cycle of 02 and C3, and two execution bus cycles C for the external device.
I, C2, by setting the dummy state number "2" to a time greater than the recovery time q2 of the external device, access by the external device is enabled in this case as well.

In this embodiment, a register was used as the signal output means and a 3-state buffer was used as the selection means, but the present invention is not limited to this, and as the signal output means, any device such as a counter that can set numerical values may be used. Any means may be used, and the selection means may be any means capable of selecting a signal such as a transfer gate.

〔Effect of the invention〕

As explained above, in this invention, when accessing an external device with a recovery time, +13jj
Since a dummy state is inserted between hash cycles for i&, and no bus cycle is activated during that time, external devices can be accessed continuously while satisfying the recovery time regardless of the software, and the program does not require any extra This eliminates the need to add instructions, prevents the program from increasing in size, and allows all processing to be performed using only the necessary execution software.

[Brief explanation of drawings]

FIG. 1 shows the configuration of the data processing device according to the present invention. FIGS. 2 and 3 are bus cycle diagrams showing the operation of the data processing device, and FIG. 4 is a conventional data processing device. 5 and 6 are pass cycle diagrams showing the operation of a conventional data processing device. 1)...Data processing bag W n...Register 18.
...3-state buffer In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa 1) Data processing device 17 Register 18-3 State buffer 1 Figure 3 Figure 4 Figure 1. Condolences 5 Condolences 6 Drawing procedure amendment (voluntary) 2. Name of the invention Data processing device 3. Name of the person making the amendment within Mitsubishi Electric Corporation (7375) Patent attorney Masuo Oiwa (Mjiko 03 (213) 3421 Patent Department ) ・2'
-'-1 5. Column 6 of "Detailed Description of the Invention" of the specification to be amended, contents of the amendment +1+ In the first line of page 3 of the specification, the phrase "When the instruction is transferred" is changed to ""To transfer orders," he corrected. (2) In the 20th line of the 3rd line of the specification, “Bus cycle B
2 can be started. " is corrected to "By activating bus cycle B2, the external device can be accessed normally." (3) In the 1st line of page 4 of the specification, [1 here is corrected to ``here''. (4) In line 12 of page 5 of the specification, the words "continuously" should be corrected to "continuously." (5) In lines 12-13 of page 6 of the specification, the phrase "The command sent" is corrected to "The command is." (6) In the 13th line of page 9 of the specification, rcl and C2J are corrected to rC2 and C3j. that's all

Claims (1)

[Claims] (1) In a data processing device that transfers data to and from an external device using a bus cycle, a signal output means that outputs a signal that inserts a non-execution state that does not start a bus cycle between successive bus cycles; 1. A data processing device comprising: selection means for selecting a signal output from the signal output means based on a predetermined signal.