JPH0230216A - Ttl circuit - Google Patents

Abstract

PURPOSE:To improve an output waveform of an output transistor(TR) and to quicken its processing operation by providing an auxiliary TR assisting the TR action of a couple of TRs in Darlington connection. CONSTITUTION:A collector of an auxiliary TR Q15 and a cross point of an emitter and a base of TRs Q12, Q11 in Darlington connection are connected and a base of the TR 15, is connected to the emitter of the TR Q14. With an output level changing from 'H' to 'L', since the auxiliary TR Q15 is connected in parallel with a series circuit comprising a diode D11 and a TR Q14, the level of the TR Q14 changes from 'H' into 'L' thereby extracting the electric charge without any inversion with respect to the polarity of an output TR Q13 till the clamp potential of the auxiliary TR Q15 even after the charge absorption depending on the base capacitance of the TR Q11 by components D11, D12, R14. Thus, a sharp descending toward the 'L' level is attained without causing an unsharpened part in the output waveform.

Description

[Detailed Description of the Invention] [Summary] TTL circuits, especially logic circuits that combine bipolar transistors (Trans istor)
Regarding the improvement of the operational function of the istor-Logic), when the output level changes from r In order to improve the performance and speed up the processing operation, the present invention is equipped with a pair of Darlington-connected off-buffer transistors, an output transistor, a phase splitter transistor, a level shift diode, and an operating resistance system. In the TTL circuit, an auxiliary transistor is provided to assist the transistor operation of the off-buffer transistor.

[Industrial application field]

The present invention relates to a TTL circuit, and more specifically, a logic circuit combining bipolar transistors (Transistor-Transistor-
Logic).

In recent years, gate arrays and I10 interfaces.

In level conversion circuits and the like, there is a demand for TTL circuits (logic circuits) made up of bipolar transistors with high current amplification factors.

However, when the output level changes from rH to "L",
In particular, there is a problem in that the fall of the output waveform becomes slow and high-speed logic (operation) cannot be performed.

Therefore, there is a demand for improving the output waveform of the TTL circuit and increasing its speed.

[Conventional technology]

7 and 8 are explanatory diagrams related to the conventional example, and FIG. 7 shows a diagram illustrating a TTL circuit according to the conventional example.

In the figure, Q11Q is a pair of Darlington-connected off-buffer transistors, Q is an output transistor, Q4 is a phase splitter transistor %DI is a speed-up diode (Schottky diode) D
□ is a pull-down diode (Schottky diode)
, R+, Ra.

The R word, Ra, is an operating resistance system, Vee is a power supply, GND is a grounding line, IN is an input, and OUT is an output. Note that the transistor Q11Q11Q is a bipolar transistor with a Schottky function.

These constitute a TTL circuit, and its function is to
Amplify the change from “L” to rH of N and send rH to the output OUT.
,→[It transmits the change in LJ.

FIG. 8 is a diagram illustrating problems related to a conventional TTL circuit.

In the figure, the vertical axis is the output level, and the output is 0 UTV,
(v) is shown. The horizontal axis is time L(s).

Note that A is the rounded part of the waveform, and the output level is "H".
→ This occurs when changing to "L". This is the first
The reason for this is that the off-buffer transistor Q is Darlington-connected with other transistors Q and operates at a large current, so the area of the transistor is large due to the allowable current etc. This increases the base capacitance ccb. When turning off the base capacitor, it takes time to discharge (remove) the charge accumulated in the base capacitor, and the waveform becomes dull transiently.

In addition, as a second cause, the off-buffer transistor Q
The base potential Il of the output transistor Q3 is lower than the sum of the base potential Il of the output transistor Q3, the saturation potential vcts of the collector of the phase splitter transistor Q4, and the Schittky potential VF of the speed-up diode D (for example, As Vcc=5(v), V□, -0,
8 (V), Vcts 0.4 (V), VF-0
, 4(v), then V□+ =Vsts +Vcts
+VF=1.6 (v) or less), the equivalent resistance r4 of the phase splitter transistor Q4 is added to the equivalent resistance r6 of the speed-up diode DI, and the equivalent resistance (r4+
r,) increases, the equivalent discharge resistance of the off-buffer transistor Q1 increases, and the time constant limited by the base capacitance CCb and the equivalent discharge resistance (ra+rn) increases, and the OFF of the off-buffer transistor Q1 increases. This causes a waveform rounding part A in the output level.

The present invention was created in view of the problems of the conventional example, and is designed to proactively remove the charge that depends on the base capacitance of the off-buffer transistor when the output level changes from rH to "L". The present invention aims to provide a TTL circuit that can improve the output waveform and speed up its processing operation.

[Means to solve the problem]

The TTL circuit of the present invention has a principle configuration as shown in FIG. 1 and one embodiment thereof in FIG. 1 and FIGS. 2 to 6, respectively.
t r * Q It, output transistor Q13, phase splitter transistor Q14, speed-up diode D, and pull-down diode I)l
z and the operating resistance system Rtl+ R11+R1! , R14
A TTL circuit comprising: an auxiliary transistor QIS that assists the transistor operation of the off-buffer transistor Q; a pair of off-buffer transistors Q11 connected to the emitter and connected to the collector of the auxiliary transistor Q+s;
, is connected to the Q-th base-emitter junction, and the emitter of the auxiliary transistor Qls is connected to the ground line GND.
The second circuit is connected to the output transistor Q + s to drain the charge of the off-buffer transistor Q + s, and the base of the auxiliary transistor Q + s is connected to the phase splitter transistor Q + a. A pair of off-buffer transistors Q + + connected to the base of the auxiliary transistor Q15 and having a Darlington connection to the collector of the auxiliary transistor Q15.
The emitter of the auxiliary transistor Q + s is connected to the base-emitter junction of the auxiliary transistor Q + Q lz, and the emitter of the auxiliary transistor Q + The third circuit is characterized in that the charge of the buffer transistor Q + + is discharged, and the third circuit is connected to the base of the auxiliary transistor Q + s to the base of the phase splitter transistor Q + a, and the collector of the auxiliary transistor Q + s is connected to a Darlington. A pair of off-buffer transistors Q +
＋＋Ql! The emitter of the auxiliary transistor Q r s is connected to the base of the output transistor Q + s, and the emitter of the auxiliary transistor Q + s is connected to the base-emitter junction of the off-buffer transistor Q + It is characterized by removing electric charge and achieves the above purpose.

[Effect]

According to the invention, the off-buffer transistor Q + +
Auxiliary transistor QCs that assists the transistor operation of
Equipped with:

Therefore, the off-buffer transistor Q transfers the charge depending on the total large capacitance to the phase splitter transistor Q.
, and the output transistor Q r s to operate in the same phase and can be extracted at high speed.

This makes it possible to quickly lower the output waveform especially when the output level changes from "H" to 'LJ, eliminate the generation of the conventional output waveform rounded portion, and improve the output waveform.

Also, according to the first circuit, the auxiliary transistor QIS is connected in parallel with the series circuit of the speed-up diode DI1 and the phase splitter transistor Q+a, and in particular the equivalent resistance of DI+ plus the internal resistance of Ql4 Regarding the time constant formed by the discharge resistor and the base capacitance of the off-buffer transistor, charge can be extracted in phase with the output transistor Q + s until the clamp potential of QIS is reached.

As a result, it is possible to sharply fall to the "L" level without generating a waveform rounding part in the output waveform as in the conventional case.

Furthermore, according to the second circuit, the auxiliary transistor Q r
s is connected in parallel with the phase splitter transistor Q t a.

For this reason, Ql4 and Q + s are operated in the same phase,
When the output level rHJ → “L” changes, the operating threshold voltage vll of Ql and the clamp potential v cis of Q r s
The charge accumulated in the base capacitance of Q can be extracted up to the potential that is the sum of Q and Q.

As a result, in the second embodiment, compared to the first embodiment,
Since the charge removal operation of Q can be started at the same time as the operation of Q15 starts, it is possible to speed up the fall of the waveform by the operating time of Q + a.

According to the third circuit, the emitter of the auxiliary transistor Q,s is connected to the base of Ql3.

Therefore, Q + s and Q operate in series, and Q +
The base current of 3 is Q, the charge that has started to be removed, and the load resistance RI! It becomes the sum of the charges appearing in , and this makes it possible to operate Q + s at high speed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 6 are diagrams for explaining the TTL circuit according to the embodiment of the present invention, and FIG. 2 is a diagram for explaining the TTL circuit according to the first embodiment of the present invention.
A diagram illustrating an L circuit is shown.

In the figure, Q is an off-buffer transistor consisting of, for example, an npn-type bipolar transistor, whose collector is connected to the power supply line Vcc (=5 (V)) via a load resistor (collector resistor) R61, and its emitter is connected to the output O
Connected to UT.

Further, Q + t is a bipolar transistor with a Schottky function, and is connected to Q l 1 in a Darlington manner to form a pair of off-buffer transistors. In addition, the Darlington connection is Q1! The collector of and the collector of Q are connected, and QI! The emitter of is connected to the base of Q, and the current amplification factor of Q is h
If the current amplification factor of rt++Q+* is hFit, this connection method is expressed as the product of both.

Further, Q + s is an output transistor, which is an npn type bipolar transistor with a Schottky function. Note that the collector is connected to the output OUT, and the base is connected to Q.
+ is connected to the emitter of <, and the emitter is connected to the ground wire GN
Connected to D.

Note that Q + a is a phase splitter transistor, whose collector is connected to the power supply line VCC via a load resistor R1□, whose base is connected to the input IN, and whose emitter is connected to the ground line via I)tt and a resistor RI4. Connected to GND.

Also, D is a speed-up diode (Schottky diode), D+z is a pull-down diode (Schottky diode), and the base charge of Q and Q +
This is a diode that removes the base charge of 3.

Q + s is an auxiliary transistor that assists the operation of the off-buffer transistor Q + +.

Note that in the embodiment of the present invention, an npn type bipolar transistor with a Schottky function is used.

Moreover, the connection method is that the collector of Q+s is connected to the off-buffer transistor Ql by Darlington.

Connect the emitter-base intersection of Qll, make the load resistor R13 function as a collector resistor, connect the base of Q + s to the emitter of phase splitter transistor Q + 4, and connect the emitter of Q Ia to the ground line GND. It is something to do.

In addition, bipolar transistor Q with Schottky function
+ t −Q + s is set to 0 for the base potential V, −1 V, for example, so that the transistor does not become saturated.
．． It has a function of clamping 4V and setting the collector potential to Vc-0.6V.

Next, the operation of this circuit will be explained, including the operational function of the auxiliary transistor Q + s.

First, when the input IN is rl (J), the phase splitter transistor Q4 turns ON, current flows through the load resistor R, a voltage drop occurs, and the off-buffer transistor Ql!
The base potential V□1 of becomes below the operation threshold voltage (DC 0.8V), Q +t is rOFF, +L11Q is also rOFF, L, auxiliary transistor Q + s and output transistor Q1. The output is OUT.

Also, input! When N is “L”, load resistance R1! Since no voltage drop occurs in , the off-buffer transistors output rON, L, and rH.

Note that when the output level changes from "H" to "L", the auxiliary transistor Q15 is connected to the speed-up diode D.
In particular, Q10 is connected in parallel with the series circuit of I+ and phase splitter transistor Q+a.
H"-"L", Dl15Q14. Paste! +R1
Even after most of the charge absorption operation dependent on the base capacitance of Q is completed due to Q4, the equivalent discharge resistance is the equivalent resistance of D plus the equivalent resistance of QI4, and the base capacitance of the off-buffer transistor QI+. With respect to the time constant formed by , the charge can be extracted in phase with the output transistor Q + s until the clamp potential of Q + s (0,4v) is reached.

As a result, it is possible to sharply fall to the "L" level without generating a waveform rounding part in the output waveform as in the conventional case.

FIG. 3 is a diagram illustrating a TTL circuit according to a second embodiment of the present invention.

In the figure, parts with the same reference numerals as those in the first embodiment have the same functions, so their explanation will be omitted. Note that the connection of the collector of the auxiliary transistor Q + s is the same as in the first embodiment, but the connection method of the base and emitter is different.

That is, the base of the auxiliary transistor Q r s is connected to the base of the phase splitter transistor Q + 4, and the emitter of QIS is grounded via the load resistor IR15! Connected to IGND.

Therefore, Q and Q + s are connected in parallel and operated in the same phase, and when the output level rH, → "L" changes, the operating dark value voltage v, ! of the output transistor Q13 changes. (';0.
8v) and the clamp potential of Q + s Vcts (=
The charge accumulated in the base capacitance of the off-buffer transistor can be discharged up to the potential (!=i1.2v) which is the sum of 0.4v) and 0.4v).

As a result, after the operation of Q Ia, Q +
Compared to the first embodiment, which requires an operation time to start the operation of s and turn QIl to rOFFJ, in the second embodiment,
Since the discharge of charge from the transistor Q starts at the same time as the operation of Q + a + Q + s starts, it is possible to speed up the fall of the waveform by the operation time of Q r a according to the first embodiment. becomes.

FIG. 4 is a diagram illustrating a TTL circuit according to the third embodiment.

In the figure, parts with the same reference numerals as those in the first embodiment have the same functions, so their explanation will be omitted. Note that the collector and base connections of the auxiliary transistor QCs are the same as in the second embodiment, but the emitter connection method is different.

That is, the emitter of the auxiliary transistor Q + s is the output transistor Ql! connected to the base of.

Therefore, Q + s and Q + i operate in series and in phase with the phase splitter transistors Q and 4. Therefore, the output transistor Q l 3 is Q
Q13 can be operated at high speed by using the charge of r + and the charge appearing on the load resistor R1 as a base current.

This makes it possible to rapidly remove the charge from Q + +, thereby making it possible to sharply lower the output waveform.

FIG. 5 is a diagram illustrating output waveforms according to each embodiment of the present invention.

In the figure, the vertical axis is the output level and represents the potential of the output OUT. The horizontal axis also represents time. Note that the output waveform falls sharply when the output level changes from rH to "LJ" due to the connection of the auxiliary transistor Qls.

FIG. 6 is a diagram comparing output waveforms according to each embodiment of the present invention and a conventional example.

In the figure, the solid line section A indicates the output waveform according to the present invention, and the dashed-dotted line section B indicates the output waveform according to the conventional example.

Therefore, by connecting the auxiliary transistor Q r s, the output waveform can be improved.

In this way, the auxiliary transistor QIs is provided to assist the operational function of the off-buffer transistor QII.

Therefore, the charge that depends on the base capacitance of QIl is
It operates in the same phase as +4 and the output transistor Qrs, and can be extracted at high speed.

This makes it possible to quickly lower the output waveform especially when the output level changes from rH to "L", eliminate the waveform rounding part that occurs in the conventional case, and improve the output waveform.

〔Effect of the invention〕

As described above, according to the present invention, by connecting the auxiliary transistor of the TTL circuit, it is possible to actively drain the charge from the off-buffer transistor.

Therefore, it is possible to improve the output waveform and increase the speed of transistor operation, thereby making it possible to improve the operational function of the TTL circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle configuration of a TTL circuit according to each embodiment of the present invention. FIG. 2 is a diagram explaining a TTL circuit according to a first embodiment of the present invention. FIG. 4 is a diagram illustrating a TTL circuit according to a third embodiment of the present invention. FIG. 5 is an output diagram according to each embodiment of the present invention. FIG. 6 is a diagram for explaining waveforms, FIG. 6 is a diagram for comparing output waveforms according to each embodiment of the present invention and a conventional example, FIG. 7 is a diagram for explaining a TTL circuit according to a conventional example, and FIG. 8 is a diagram for explaining a TTL circuit according to a conventional example. FIG. 2 is a diagram illustrating problems related to a conventional TTL circuit. (Explanation of symbols) Q I+ Qz+ (L++ (Lx...off buffer transistor, Q11Q, ff...output transistor, Q11Q11
・・・Phase splitter transistor, D+, D,・
...Speed-up diode, Dz, D, t...Pull-down diode, R6~R11R11~RI5...
・Load resistance (operating resistance system), Q + s...Auxiliary transistor, A...Waveform rounding part, VCC...Power line, GND...Grounding line, IN...Input, OUT... Output Q11Q11... npn type bipolar transistor,
Q2~Q11Q11~Q1s... NPN type bipolar transistor with Schottky function.

Claims (4)

[Claims] (1) A pair of Darlington-connected off-buffer transistors (Q_1_1, Q_1_2), an output transistor (Q_1_3), a phase splitter transistor (Q_1_4), and a speed-up diode (D_
1_1), a pull-down diode (D_1_2),
Operating resistance system (R_1_1, R_1_2, R_1_3, R
_1_4), an auxiliary transistor (Q_1_5) that assists the transistor operation of the off-buffer transistor (Q_1_1);
A TTL circuit characterized by being provided with. (2) a pair of off-buffer transistors (the base of the auxiliary transistor (Q_1_5) is connected to the emitter of the phase splitter transistor (Q_1_4), and the collector of the auxiliary transistor (Q_1_5) is Darlington-connected;
The off-buffer transistor (Q_1_1) is connected to the base-emitter junction of the auxiliary transistor (Q_1_1, Q_1_2), and the emitter of the auxiliary transistor (Q_1_5) is connected to the ground line (GND). 2. The TTL circuit according to claim 1, wherein the TTL circuit removes the electric charge of ). (3) A pair of off-buffer transistors (the base of the auxiliary transistor (Q_1_5) is connected to the base of the phase splitter transistor (Q_1_4), and the collector of the auxiliary transistor (Q_1_5) is Darlington-connected.
The emitter of the auxiliary transistor (Q_1_5) is connected to the ground line (GND) via the operating resistance system (R_1_5), and the phase splitter transistor (Q_1_4) The off-buffer transistor (Q_1_1)
2. The TTL circuit according to claim 1, wherein the TTL circuit removes the electric charge. (4) A pair of off-buffer transistors (the base of the auxiliary transistor (Q_1_5) is connected to the base of the phase splitter transistor (Q_1_4), and the collector of the auxiliary transistor (Q_1_5) is connected to Darlington.
Q_1_1, Q_1_2), the emitter of the auxiliary transistor (Q_1_5) is connected to the base of the output transistor (Q_1_3), and shares the phase splitter transistor (Q_1_4) with the off buffer. The TTL circuit according to claim 1, characterized in that the charge of the transistor (Q_1_1) is discharged.