JPH0230175A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To realize an integrated circuit having a capacitor whose withstand voltage characteristic is excellent by a method wherein an insulating layer situated between a third-layer wiring part as an upper-part electrode and a first-layer wiring part as an extraction wiring part of a lower-part electrode is formed of two layers and a pattern of the upper-part electrode is shaped so as to stretch to be wider than a pattern of the lower-part electrode. CONSTITUTION:A first-layer wiring part 021 is provided on the surface of a semiconductor substrate 001 via a first insulating layer 011; a second insulating layer 012 having an opening part on the first-layer wiring part 021 is provided on it; a second-layer wiring part 022 covering said opening part is provided on it; a third-layer wiring part 023 having a size covering an area of the second- layer wiring part 022 is provided on the upper layer; a capacitor formed of the second-layer wiring part 122 and the third-layer wiring part 023 is provided. Thereby, even when an ion milling crack 101 is formed along a periphery of the third-layer wiring part 023, a sufficient thickness of the insulating layer is secured because the second insulating layer 012 exists under it; the capacitor whose withstand voltage characteristic is excellent is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuit devices, and more particularly to capacitors formed within integrated circuit devices.

[Conventional technology]

A conventional capacitor in an integrated circuit device used in a high frequency band will be explained with reference to FIGS. 5 and 6.

As shown in the cross-sectional view in FIG. 5, there is a first insulating layer 011 on a semiconductor substrate 001, a patterned first layer wiring 021 is formed on it, and a second insulating layer 012 is formed on it. A second layer wiring 022 is formed so as to overlap with the first layer wiring 021 only in a portion where a capacitor is to be formed thereon.

A plan view thereof is shown in FIG. 6, in which a first layer wiring 021 and a second layer wiring 022 are formed so as to partially overlap, forming a capacitor. In the capacitor portion, the second layer wiring 022 is made larger in area than the first layer wiring 021 so as to cover it. In integrated circuit devices used in this type of high frequency band, the thickness of the top layer wiring metal is set to several micrometers by plating or the like in order to reduce transmission loss within the integrated circuit device. The capacitor is formed by forming an insulating film between an upper layer of wiring metal and a lower layer of wiring metal to a predetermined thickness.

[Problem to be solved by the invention]

The capacitors used in the conventional integrated circuits mentioned above are
Since the thickness of the second layer wiring 022 was increased by a process such as plating, when forming the pattern of the second layer wiring 022 by ion milling etc., This often results in the dielectric film being dug somewhat thinner. For this reason, the second layer wiring 022 and the first layer wiring 02
In the capacitor constructed as shown in FIG. 1, the withstand voltage characteristics are dominated by the thin portion of the dielectric film along the periphery of the pattern of the second layer wiring 021, and sufficient withstand voltage characteristics cannot be obtained. For this reason, the second
The pattern of the layer wiring 022 was made wider than the first layer wiring pattern, and the thinner dielectric film was prevented from being formed on the first layer wiring as much as possible. However, since the first layer wiring of the capacitor must be connected to other circuit elements, the first layer wiring must be placed across the edge of the second layer wiring in this area. Since the capacitor cannot obtain sufficient withstand voltage characteristics, it has the disadvantage that the withstand voltage characteristics of the capacitor are not sufficient.

[Means to solve the problem]

The integrated circuit device of the present invention has a first layer wiring formed on the surface of a semiconductor substrate via a first insulating layer, and a second insulating layer having an opening above the first layer wiring, A third insulating layer is provided thereon to cover the opening, a third insulating layer is provided to cover the entire opening, and a third insulating layer is formed on the third insulating layer to cover the area of the second layer wiring. The device has three layers of wiring, and has a capacitor formed by the second layer wiring and the third layer wiring.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention.

001 is a semiconductor substrate, 011 is a first insulating layer, 012 is a second insulating layer, 013 is a third insulating layer, 021 is a first layer wiring,
022 is a second layer wiring, 023 is a third layer wiring, and 101 is an ion milling scratch. As is clear from the figure, even if an ion milling scratch 101 is formed along the periphery of the third layer wiring, which is the upper electrode of the capacitor, there is also a second insulating layer 012 underneath, which is the lower electrode of the capacitor. Second
Since the lead wire from the layer wire 022 is the first layer wire 021, there is a sufficient insulation layer thickness of 1iI between the upper electrode and the lower electrode or the lead wire of the capacitor. is maintained, resulting in a capacitor with good withstanding voltage characteristics.

FIG. 2 is a plan view of the embodiment of FIG. 1. First layer wiring 0 for connecting the lower electrode of the capacitor to other circuit elements
The pattern 21 has a shape that extends wider than the pattern of the second layer wiring 022.

FIG. 3 is a longitudinal sectional view of a second embodiment of the invention.

The structure of FIG. 3 is similar to that of FIG. 1, but the top view of FIG. 3 is shown in FIG. In this embodiment, the pattern of the first layer wiring 021 for connecting the lower electrode of the capacitor to other circuit elements is narrower than the pattern of the second layer wiring 022.

The first embodiment shown in FIGS. 1 and 2 and the second embodiment shown in FIGS. 2 and 3 are the pattern of the first layer wiring 021 and the second layer wiring 02.
This is a relative difference in shape from the second pattern, and both of these serve the purpose of the present invention.

〔Effect of the invention〕

As explained above, in the present invention, the upper electrode of the capacitor is the third-layer wiring, the lower electrode is the second-layer wiring, the lead-out wiring of the lower electrode is the first-layer wiring, and the third-layer wiring which is the upper electrode and the lower It has two insulating layers between the first layer wiring, which is the lead-out wiring of the electrode, to increase the withstand voltage, and the upper electrode pattern is shaped to protrude wider than the lower electrode pattern, resulting in good withstanding voltage characteristics. This has the effect of realizing an integrated circuit using capacitors.

[Brief explanation of the drawing]

1 is a longitudinal sectional view of a first embodiment of a capacitor formed in an integrated circuit of the present invention, FIG. 2 is a plan view of FIG. 1, and FIG.
4 is a plan view of FIG. 3, FIG. 5 is a longitudinal sectional view of a capacitor formed in a conventional integrated circuit, and FIG. 6 is a longitudinal sectional view of a second embodiment of the present invention. FIG. 5 is a plan view of FIG. 5; 001... Semiconductor substrate, 011... First insulating layer, 012... Second insulating layer, 013...
...Third insulating layer, ...First layer wiring, 22...Second layer wiring, 023...Third layer wiring, 1... Ion milling scar.

Claims (1)

[Claims] A first layer wiring is formed on the surface of the semiconductor substrate via a first insulating layer, and a second insulating layer having an opening on the first layer wiring is formed thereon to cover the opening. It has a second layer wiring, a third insulating layer covering the whole thereon, and a third layer wiring having a portion having a size that covers the area of the second layer wiring on the upper layer, An integrated circuit device comprising a capacitor formed by a second layer wiring and the third layer wiring.