JPH02296366A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02296366A
JPH02296366A JP1117059A JP11705989A JPH02296366A JP H02296366 A JPH02296366 A JP H02296366A JP 1117059 A JP1117059 A JP 1117059A JP 11705989 A JP11705989 A JP 11705989A JP H02296366 A JPH02296366 A JP H02296366A
Authority
JP
Japan
Prior art keywords
gate electrodes
layer gate
layer
semiconductor substrate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1117059A
Other languages
Japanese (ja)
Other versions
JP2516428B2 (en
Inventor
Koji Fujimoto
Masatoshi Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1117059A priority Critical patent/JP2516428B2/en
Publication of JPH02296366A publication Critical patent/JPH02296366A/en
Application granted granted Critical
Publication of JP2516428B2 publication Critical patent/JP2516428B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate ion implantation by etching a second layer gate electrode material formed on a semiconductor substrate surface, an insulating layer surface, and the upper surface of first layer gate electrodes as far as the upper surface of the first layer gate electrodes, eliminating the insulating layer, and forming a second layer gate electrodes between the first layer gate electrodes.
CONSTITUTION: After an insulating layer 6 is formed on the surface of a semiconductor substrate and the surface of a first layer gate electrodes 5 formed on the said substrate surface, the insulating layer 6 is anisotropically etched, and left only on the side surfaces of the first layer gate electrodes 5; a second layer gate electrode material 8 is deposited on the surface of the left insulating, layer 6, the upper surface of the first layer gate electrodes 5, and the surface of the semiconductor substrate 1; said material 8 is etched almost as far as the upper surface of the first layer gate electrodes 5; then the left insulating layer 6 is eliminated, thereby forming a second layer gate electrode 8a between the first layer gate electrodes 5. As a result, the first layer gate electrodes 5 and the second layer gate electrodes 8a do not overlap, so that unevenness is not present on the upper surface of the semiconductor substrate 1 and a flat structure is obtained. Thereby ion implantation is facilitated.
COPYRIGHT: (C)1990,JPO&Japio
JP1117059A 1989-05-10 1989-05-10 Method for manufacturing semiconductor device Expired - Fee Related JP2516428B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1117059A JP2516428B2 (en) 1989-05-10 1989-05-10 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1117059A JP2516428B2 (en) 1989-05-10 1989-05-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02296366A true JPH02296366A (en) 1990-12-06
JP2516428B2 JP2516428B2 (en) 1996-07-24

Family

ID=14702412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1117059A Expired - Fee Related JP2516428B2 (en) 1989-05-10 1989-05-10 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2516428B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008093A (en) * 1997-02-03 1999-12-28 Sharp Kabushiki Kaisha Method of making a mask ROM

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51151089A (en) * 1975-06-20 1976-12-25 Matsushita Electric Ind Co Ltd Manufacturing method of a semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51151089A (en) * 1975-06-20 1976-12-25 Matsushita Electric Ind Co Ltd Manufacturing method of a semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008093A (en) * 1997-02-03 1999-12-28 Sharp Kabushiki Kaisha Method of making a mask ROM

Also Published As

Publication number Publication date
JP2516428B2 (en) 1996-07-24

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