JPH02289010A - Information processor - Google Patents

Abstract

PURPOSE:To attain the process of data containing a tag part by connecting a tag storage part assigned to the same address of a main storage part to a common bus and connecting only a tag data transfer part to a CPU part which treats the data containing a tag via a connection control means. CONSTITUTION:When the data containing a tag is read out to an information processor, a tag storage part (d) outputs only the tag part of the data to a CPU part (c) as the tag data through a connection control means (e). A main storage part (b) outputs the main data on the same address as the tag data to the part (c) through a data line of a common bus (a). The part (c) connects the tag data to the main data and processes them as the data containing a tag of a single word. When the data containing a tag is written, the part (c) outputs the data on only the tag part of the data containing a tag to the part (d) through the means (e). At the same time, the main data part of the data containing a tag is outputted to the same address as the tag part of the part (b) through the data line of the bus (a). As a result, an inexpensive and standard main storage or an input/output device is applied on the bus (a) and at the same time the data containing a tag part can be processed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device, and particularly to an information processing device that processes data having a tag portion.

(Prior Art) Conventionally, in computers that exclusively execute so-called symbolic processing languages such as LISP and Prolog, in addition to the conventional value part, a tag part is added to 5 data.The tag part is generally It consists of about 4 to 8 bits, and a code indicating the attribute of the value part is written there.

Fig. 3 is a block diagram showing the structure of one word of a conventional calculator having a tag part, and in Fig. 3, 100 is a value part of 3.
2 bits, 101 is a tag part consisting of 8 bits. Therefore, the data of the - word consists of 40 bits. In this conventional example, the data register and main memory are all constructed of 40-bit words.

FIG. 4 is a conventional hardware configuration diagram having a tag section. In FIG. 4, 1 is a CPU section having a tag section that handles data including the tag section; 2 is a main storage section having a tag section; 3 is a human output unit that controls the input/output device, and 4.7
are control lines each having a width of 32 bits between each part, 5
．． 8 is an address line with a width of 32 bits between each section, 6 is a data line with a width of 32 bits between the human output control section 3 and the CPU section 1, and 9 is a data line between the 020 section 1 and the main memory section 2. The data line 9 has a width of 40 bits because it is necessary to transfer data including the tag part.

Next, the operation of this conventional example will be explained using FIG. 4. In Figure 4, first, the CPU section! Memory read from address ll! The address is transferred to the main memory unit 2 via the data bit 8, and the 40-bit width data of the address is transferred to the 020 part 1 via the data llQ9. During this time, command transfer, timing control, etc. are performed through the control line 7. On the other hand, the human output pU of printer '8 (not shown)
To write data to the device, the device address is similarly specified through the address line 5, and old data is sent via the data line 6. As with the transfer with the main storage unit 2, timing and other controls are performed using the control line 4.

At this time, the human output control section 3 does not require a tag section, only the value section of the data. Therefore, the bit width of the data line 6 is 32 bits for the value part only, and data transfer between the main memory part and the CPU part requires a transfer width of 40 bits including the tag part.

On the other hand, in recent years, there has been a noticeable trend in the hardware configuration of computers by connecting components such as a CPU section and a main memory section using a common bus, thereby making each component independent and common. FIG. 5 is a configuration diagram of a conventional example showing the connection of a common bus. In the figure, 11 is a CPU section (32 bits), 12 is a main memory section (32 bits x NiΔ), 13 is an output control section,
! 4, 15, and 16 are common bus signal lines, 14 is a control line, 15 is an address line, and 16 is a data line. Further, CPU15 (32 bits) 11 is a general-purpose CPU, and unlike the 020 part 1 (40 bits) shown in FIG. 4, it does not have a tag part. The main memory section 12 also does not have a tag section and is composed of 32 bits per word. Therefore, data line 16 is 32 bits wide. In this way, if each element constituting a computer is designed according to the common bus of 14.15.16, each component can be compatible with other machines, and both manufacturers and users can There are great benefits for.

Therefore, it is desirable that the CPU section that handles tagged data as shown in FIG. 4 be also connected to such a common bus.

Further, as a conventional example, Japanese Patent Application Laid-Open No. 182756/1983 has been disclosed. This conventional example relates to a cache memory between an information processing device and a main memory, and does not relate to the main memory. Furthermore, the tag storage circuit 51 in FIG. 3 of this conventional example is generally referred to as a cache directory memory, and is used only within the cache mechanism to manage cache hits/misses. Data whose contents are read and processed by the CPU is not stored.

That is, in this conventional example shown in FIG. 3, the tag read data is manually inputted only to the comparison circuit 53 and used only for condition determination, and the tag read data is not connected to the CPU.

(Problems to be Solved by the Invention) As described above, in the conventional example, the CPU section that handles the tagged data shown in FIG. When connecting to the common bus, there was a problem that it could not be easily realized because the data line of the common bus did not have a signal line for connecting the tag, and the main memory section connected to the common bus did not have a tag section. .

This invention was made in order to eliminate the conventional r::t point of reference as described above, and connects the tag memory section assigned to the same address as the main memory section to a common bus, and transfers only that data. CPU that handles tagged data at stage f of connection control
It is an object of the present invention to provide an information processing device that is connected to a tag section, uses an inexpensive and standard main memory and input/output device of a common bus, and is capable of data processing having a tag section.

[Means to solve the problem]

Therefore, in the present invention, there is provided a common bus consisting of a control line, an address line, and a data line, and a main memory section configured with a bit width equal to the data transfer width of the common bus, and connected to each line of the common bus. and a tag portion consisting of a bit width of the data transfer width and a bit width of a portion exceeding the data transfer width, and is connected to each line of the common bus.
a U section, a tag storage section that has the same bit width as the tag section, is assigned the same address as the nj main storage section, and is connected to the control line and the address line; the CPU section and the tag. The above objective is achieved by an information processing apparatus which is provided with a connection control means that connects a storage section and controls the connection of tag data in the tag storage section with data in the main storage section.

[Effect]

In the case of reading tagged data to the information processing apparatus according to the present invention, the tag storage section outputs only the tag part of the tagged data as tag data to the CPU section through the connection control means, and the main storage section outputs only the tag part of the tagged data to the CPU section. The main data at the same address is output to the CPU through the data line of the common bus. The CPU unit concatenates these tag data and main data and processes them as -5 tagged data.

In addition, in the case of a loading of tagged data, the CPU outputs the tag data of only the tag part of the tagged data to the tag storage part through the connection control means, and the main data part of the tagged data is connected to the data line of the common bus. It is output to the same address as the H tag section of the main storage section.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram showing the relationship between the main storage section and tag storage section in FIG. 1 and linked data. In FIG. 1, the same reference numerals as in the conventional example indicate the same or corresponding parts. In addition, (a) is the control line 14. Address line! 5
A common bus (B) consisting of a data line 16 and a data line 16 is the main memory section 12, and has a width of 32 bits, which is the bit width of the data transfer width of the common bus (A).
It is connected to each line in (b).

Further, (c) is the CPU section 17, which has a tag section with a bit width of 32 bits of the data transfer width and a bit width of 8 bits in a portion exceeding the transfer width, for a total of 40 bits.
It has a bit width and is connected to each line of the common bus (A). (D) is a tag storage unit 18, which has the same bit width as the tag unit, 8 bits, has the same address allocation as the main storage unit 12, and has a control line 14 and an address line 15. is connected to. (E) is the connection control means, which is the CPU section! It is composed of a tag data line 19 that connects the tag storage section 7 and the tag storage section 18 to store and write tag data, and a dedicated control line 23 that exclusively controls this line, and connects and controls the tag storage section 18 and the 021 section 17. It is something.

Next, the operation of this embodiment will be explained using FIGS. 1 and 2.

First, in the case of reading the main memory from the 021 unit 17, a read command is sent through the control line 14, and the address of the main memory is sent to the respective buses through the address fi15. The same address is assigned to the main memory section 12 and the tag memory section 18 as described above. In the main storage section 12, the contents of the selected address are read out and sent to the data line 16. A signal indicating completion of reading is also sent to the control 4114 at the same time. The tag storage unit 18 also sends the contents of the selected address to the tag data 4919. A signal indicating the completion of gun ejection is also sent to the dedicated control line 23 at the same time. The 021 section 17 takes in the data on the data line 16 and the data on the tag data line 19 at the same time, connects them, and treats them as -5 tagged data. FIG. 2 is a diagram showing the relationship between data in each storage section and data handled by the CPU section.
indicates the content of 8 bits x N words in the tag storage unit 18, and 21
indicates the contents of a 32-bit xN word in the main memory section 12.

22 shows the contents when the CPU section 17 reads address 0011 in this state. Two data are concatenated and tagged 4
It is 0 bit data.

In addition, in the case of writing from the CPU section 17, the first eight bits of the 40-bit data on the CPU section side are sent as tag data to the tag storage section 18 via the tag data line 19, and the lower 32 bits are sent via the data line 16. The data are respectively stored in the second storage unit 12.

Note that in the embodiment, the address line 15 and the data line 16
Although the common bus (a) in which the busses are separated has been described, even if they are buses that use the same signal line in a time-sharing manner, the same operations and effects as in the embodiment described above can be achieved.

(Effects of the Invention) As explained above, according to the present invention, the tag storage section assigned to the same address as the main storage section is connected to a common lot, and only the tag data transfer is performed using the connection control means to transfer the tagged data. Since it is connected to the CPU section that handles data processing, it is possible to obtain an information processing device that uses an inexpensive and standard main memory section and input/output device on a common bus, and is capable of data processing with a tag section. .

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an information processing device according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing the relationship between the main storage section and tag storage section in FIG. 1, and linked data, and FIG. FIG. 4 is a diagram showing the configuration of one word of data, FIG. 4 is a diagram showing the configuration of a conventional information processing device that handles tagged data, and FIG. 5 is a configuration diagram of a conventional information processing device connected to a common bus. A...Common bus slot...Main storage section C...-cpu section II...Tag storage section H...Connection control means 12... ... Main memory section 13 ... Human output control section 14 ... Control line 15 ... Address line 16 ... Data line 17 ... - Cpu unit 18...Tag storage unit 19...Tag data line 23...- Dedicated control line Note that in the drawings, the same reference numerals indicate the same or equivalent parts. Figure 2

Claims (1)

[Scope of Claims] An information processing device characterized by comprising the following components (a) to (e). (a) A common bus consisting of control lines, address lines, and data lines. (b) A main memory section configured with a bit width equal to the data transfer width of the common bus and connected to each line of the common bus. (c) A CPU section having a tag section having a bit width of the data transfer width and a bit width of a portion exceeding the data transfer width, and connected to each line of the common bus. (d) A tag storage section that has the same bit width as the tag section, is assigned the same address as the main storage section, and is connected to the control line and address line. (E) Connection control means for connecting the CPU section and the tag storage section and controlling the connection of tag data in the tag storage section with data in the main storage section.