JPH02288925A - Memory controller - Google Patents

Abstract

PURPOSE:To access word data of continuous bits in the subscanning direction in one memory cycle by assigning n-number of bit data constituting one arbitrary longitudinal word and one arbitrary transverse word in a memory block to n-number of memory chips without overlapping. CONSTITUTION:The mode is switched to the longitudinal mode for access of one-byte data continuous in the transverse direction or the transverse mode for access of one-byte data continuous in the longitudinal direction by a longitudinal/transverse mode select signal line 7 inputted to a memory address conversion unit 4. Thus, arbitrary one-byte data (PnV.0, PnV.1 to PnV.7) continuous in the transverse direction and arbitrary one-byte data (P0nH, P1nH to P7nH) continuous in the longitudinal direction are accessed with addresses [(8A+nv).H +B] and [(8B+nH) V+A] respectively in one memory cycle.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a memory control device for a memory circuit that can be randomly accessed by addresses, and more particularly to a memory control device for storing image data, which uses memory space two-dimensionally. [Prior Art] In recent years, as memory chips have become larger in capacity and more highly integrated, it has become possible to install image memory capable of storing image data for one page of standard paper in facsimile machines and the like at low cost. With this, various applications such as image processing on a page basis are performed. Conventionally, in this type of apparatus, memory addressing is normally allocated continuously in the main scanning direction of regular-sized paper, and this addressing is fixed. [Problem to be solved by the invention] Conventionally, it has been difficult for this type of device to access continuous image data in the sub-scanning direction, and this has generally been done using several steps of software. This was one of the causes of performance deterioration in image processing operations. [Means for Solving the Problems] According to the present invention, a two-dimensional memory space is divided into certain words (
n bits) generated by dividing vertically and horizontally
No matter which vertical 1 word or horizontal 1 word data in a memory block consisting of n bit data is selected, the n bit data constituting the word data will be transferred to n memory chips. By having means for allocating data without duplication or omission, accessing word data with consecutive bits in the sub-scanning direction, which was conventionally performed by several steps of software, can now be accessed in one memory.
This is made possible by Zaikle. Furthermore, the memory address given to each n memory chip is determined whether the requested word data is bit continuous in the horizontal (main scanning line) direction (vertical mode) or bit continuous in the vertical (sub scanning line) direction. (horizontal mode), the state of the vertical/horizontal mode selection signal line, and the preset constants for the number of bytes in the horizontal direction and the number of bytes in the vertical direction. means for generating memory addresses to be given to each of the n memory chips from the temporary addresses obtained; and means for determining a connection pattern between the n memory chips and the n data lines constituting the external data bus. By having this, it is possible to access any one word of data in different modes for each memory cycle. The method further includes means for calculating the position of the word data requested for access within the memory block, and the connection pattern between the n memory chips and the n data lines constituting the external data lot is determined as described above. The configuration of the memory circuit is simplified by using a connection pattern that can be determined only by the calculated position, regardless of the vertical/horizontal mode settings. [Embodiment] FIGS. 1 to 15 show an embodiment of the memory circuit of the present invention and its operating principle. FIG. 1 is a block diagram of an embodiment of a memory circuit of the present invention. In this figure, 1 is a memory chip, and eight memory chips are used. One memory chip 1 may be composed of a DRAM chip or the like (with a word width of 1 bit) having a 1-bit data input/output port. Each of the eight memory chips 1 is assigned a chip number of co-07. 2 is a memory address bus for addressing the memory chips 1, and the memory address buses 2 of the eight memory chips 1 are independently supplied. 3 is a memory data line connected to the data input/output port of the memory chip 1; 4 is a memory address conversion unit. A CPU address bus 5, a standard paper size selection signal line 6, and a portrait/horizontal mode selection signal line 7 are input to this memory address conversion unit 4, and in addition to the eight sets of memory address buses 2, data A bus conversion instruction υ line 8 is output. 9 is a memory data conversion unit, and 10 is a CPU data bus. FIG. 2 shows the memory circuit of this embodiment, and shows the memory addresses when the vertical mode is selected when image data in which one pixel is represented by one bit is stored. In the figure, V is the number of lines in the vertical direction, and H is the number of bytes when the number of pixels in the horizontal direction is divided into 8-bit (1 byte) units. Here, the number of pixels in the horizontal direction is a multiple of 8, and is set so that it can be divided into bytes without remainder. memory address

[0] is the first 8 counting from the left of the top line
Refers to bit (1 byte) data, and the rightmost 1 byte data on the bottom line is assigned to the maximum memory address 1:vH-1). In this vertical mode, any 1-byte data can be generated using vertical line number a (0≦a≦v-1) counted from the top and byte number B (0≦B≦H-1) counted from the left.・■(+](
[0)≦lea −H+] ≦[v−H−1]). FIG. 3 shows the memory addresses when the horizontal mode is selected in the case where image data in which one pixel is represented by one bit is stored in the memory circuit of this embodiment. In the figure, V is the number of bytes when the number of pixels in the vertical direction is divided into units of 8 bits (1 byte), and h is the number of lines in the horizontal direction. Here, the number of pixels in the vertical direction is a multiple of 8, and is set so that it can be divided into bytes without remainder. memory address

[0] refers to the first 8 bits (1 byte) of data counting from the top of the leftmost line, and the 1 byte of data located at the bottom of the rightmost line corresponds to the maximum memory address (h-V-1 ) is assigned to. In this horizontal mode, any 1-byte data can be obtained by using the horizontal line number b (o≦b≦h) counted from the left and the byte number A (0≦A≦V-1) counted from the top. -V+A)
MO) ≦(b-V+A] ≦(h-V-1)). If the standard paper size is the same, the following relationship holds between the parameters in FIGS. 2 and 3. Number of vertical lines (pixels) and number of bytes: v=8V
Number of horizontal lines (pixels) and number of bytes: h=8H
Maximum at 1. /S: [V-H-1)E [h-V
-1)E (8V-H-1) FIG. 4 shows the concept of memory blocks in the memory circuit of this embodiment. In the figure, V is the number of bytes in the vertical direction (number of pixels divided by 8), and H is the number of bytes in the horizontal direction (number of pixels divided by 8). A memory block is a group of 64 bits, 8 bits horizontally and vertically, and the upper leftmost memory block is M. ,. The lower right memory block is represented by MV-1 and H-1. Any memory block has vertical byte number A (0
≦A≦v−i) and the horizontal byte number B (0≦
B≦H-1), it can be expressed as MA, 8. One memory block consists of 8 bytes of data. FIG. 5 shows memory block MA in vertical mode. 8 shows the addresses of 8 byte data. All these 8 addresses are [:(8A
It can be expressed as 10ny) H+B) (0≦nV≦7). Here, nV is the memory value of that byte data.
It represents the position counted from the top within blocks MA and B. FIG. 6 shows the addresses of eight byte data when the memory blocks M A and B are accessed in the horizontal mode. All these eight addresses are [:(8B+nH)・V+A](0≦n
H≦7). Here, nH represents the position of the byte data in memory blocks MA, B, counting from the left. FIG. 7 shows the arrangement of 64 bit data within one memory block. Any 1-bit data in a memory block is the number of bits ny (counted from the top)
0≦nv≦7) and the number of bits counted from the left nH (0≦n
H≦7) and can be expressed as PnV, nH (=0 or ]). Figure 8 shows any 1 accessed in portrait mode and landscape mode.
Each represents 8-bit data included in byte data. Any 1-bit data Pny within one memory block. nH is the address ((8A+nV) bow-T
10B: ], and in landscape mode, the address ((8B
+n. )・V1A). For example, bit data P2, 5 in memory blocks MA, B is at the address [(8A + 2) · H + B) in vertical mode.
It can be accessed with bit D2 of the byte data indicated by , and in horizontal mode, the address [(8B+5)・V
It can be accessed by bit D5 of the byte data indicated by +Al. FIG. 9 is a block diagram showing the configuration of the memory address conversion unit 4. In the figure, 2 is a memory address bus, 5 is a CPU address bus, 6 is a standard paper size selection signal line, 7 is a vertical/horizontal mode selection signal line, 8 is a data bus conversion instruction signal line, and 11 is a vertical/horizontal mode selection signal line. Horizontal byte count register, 1
2 is a divider, 13 is a divisor line for divider 12, 1
4 is the quotient line of the divider I2, 15 is the remainder line of the divider 12, 16 is the upper bit line of the quotient line 14 excluding the lower 3 bit width data/lotus conversion instruction signal line 8, and J7 is the subtraction line. I8 is the difference line of the subtractor 17, 19
is a multiplier, and 20 is a multiplier 19 in which the 3-pitch I/width difference line 18 is connected to the lower part and the remainder line 15 is connected to the upper part.
21 is a multiplier line for the multiplier 19, 22 is a product line for the multiplier 19, 23 is an adder,
24 is a sum line of the adder 23, and 25 is a multiplexer. Figure 10 shows that when the vertical mode is selected, the memory
This shows the contents on each signal line in the address conversion unit 4. 1] Figure 1 shows the memory shown in Figure 9 above when the horizontal mode is selected.
This shows the contents on each signal line in the address conversion unit 4. FIG. 12 shows the number of vertical bytes (■) and the number of horizontal bytes (H) stored in the vertical/horizontal byte number register 11 in the memory address conversion unit 4 shown in FIG. This shows the correspondence with the code. The signal line 6 has a width of 4 pits, and by representing the numerical value in the column of "code" in the figure with 4 pits and inputting it to the register 11, the number of vertical bytes V or the number of horizontal bytes H in the figure can be obtained. FIG. 13 shows the correspondence between each bit D7 to DO of the CPU data bus 10 and the cell numbers C8 to C7 of the memory cell 1 when the vertical mode is selected in the memory circuit of this embodiment. The code indicated by line 8 is nV (0≦ny≦
7) respectively. Similarly, FIG. 14 shows each bit D7 to Do of the CPU data bus 10 and the memory cell 1 when the horizontal mode is selected.
The correspondence with cell number C8-07 is shown for each code n14 (0≦nH≦7) of the data bus conversion instruction signal line 8. FIG. 15 is a block diagram showing the configuration of the memory/data conversion unit 9. In the figure, 3 is a memory data line, 8 is a data bus conversion instruction signal line, 10 is a CPU data bus, 31 is a decoder, and 32 is a part obtained by decoding the data bus conversion instruction signal line 8 by the decoder 31. 8 sets of buffer enable signals, 33 is a bidirectional transceiver buffer. Next, the operation of the memory circuit of this embodiment will be explained based on FIGS. 1 to 15 above. Initially in the vertical mode the memory blocks MA, B
The operation when an arbitrary 1-byte data access occurs will be explained. First, it is assumed that the portrait/horizontal mode selection signal line 7 is set to "portrait mode" and a predetermined code is set on the standard paper size selection signal line 6 in accordance with FIG. 12. An address pointing to arbitrary 1-byte data in the memory blocks MA, B in the vertical mode through the CPU address bus 5 [(8A + nv) .
When H+B: ] (0≦ny≦7) (see FIG. 10) is input to the memory address conversion unit 4, the memory address conversion unit 4 directly converts the input address to the memory via the multiplexer 25. - Send to address bus 2. In this case, a memory address with the same content is sent to all memory chips ICo-C7. The vertical/horizontal byte register 11 in the memory address conversion unit 4 divides the horizontal byte number H into a divider 12 according to the contents of the standard paper size selection signal line 6 as shown in FIG.
The divisor line for [3] is sent. The divider 12 selects the memory address [:(8A
+n v, )#H+B), number of horizontal bytes [H]
Execute division by and get the quotient [8A+nv]
[B], which is the remainder on the quotient line 14, is output on the remainder line 15, respectively. In vertical mode, the cylinder (8A
+nV), the contents of the lower 3 bits [nv:l(0≦n
y≦7) is required, and the data bus conversion instruction signal line 8
The data is sent to the memory data conversion unit 9 through the memory data conversion unit 9. The memory data conversion unit 9 receives a code [nV] (0≦nV) input through the data bus conversion instruction signal line 8.
7) using the decoder 31 to realize the correspondence between the memory data line 3 and the CPU data bus 10 according to FIG. Buffer enable signal 3
Assert 2. Through the above operations, the memory address ((8A+n v) ・H+B) is supplied to C8 to C7 of memory chip 1, and the memory data line 3 is also supplied with CPU data and
It is connected to each bit D7-Do of the bus 10, allowing memory access as shown in FIG. Next, in the transverse mode, the memory blocks M A, B
The operation when an arbitrary 1-byte data access occurs will be explained. First, it is assumed that the portrait/horizontal mode selection signal line 7 is set to "horizontal mode" and that a predetermined code is set on the standard paper size selection signal 6 in accordance with FIG. 12. Each bit data P constituting arbitrary 1-byte data in memory blocks MA and B in the horizontal mode. ,
nH-P7. nH (see Figure 8) are memory and
Each memory is allocated to one of chips C8 to C7 of chip l without duplication.
The addresses to chip 1 are different. This is because the addressing method for memory chip l is based on the vertical mode, and as shown in FIG.
address must be given. In other words, the memory address in horizontal mode [(8B0nH
)・V + A) to 8 memory addresses in vertical mode ((8A+O)・H+B) to ((8A+7)・H
+B) and generate C6~ of each memory chip 1
It is necessary to give it to C7. 8 memory in vertical mode
Conversion to address is done by constant ■ (number of vertical bytes) and constant H (
This is possible if the number of horizontal bytes) can be obtained. On the other hand, in order to determine which memory chip 1 to give each of the eight memory addresses in the vertical mode, it is necessary to
The correlation in the correspondence table between memory chips in vertical/horizontal modes and the data bus 10 shown in FIG. 4 is used. For example, memory block MA in transverse mode. 1 byte data in 8〈P' O+ 3, Pl +
3, “'P7,3> is address I: (8E+3)・
Access is requested by V+A). Here, the memory block MA in the horizontal mode of this byte data
, the position counted from the left in B is 3, so nH=3. When nH=3, 1 byte data (PO+3, P
As shown in FIG. 14, each bit data of 113, . . . P7, 3> is assigned to C8-07 of memory chip l. , 3→C4, PI, 3→C3
, P7,3→C5. Bit data P assigned to 04 of memory chip 1. , 3 are included in the uppermost horizontal byte data in memory blocks M A and B, as shown in FIG. The 0th byte data counting from the top is addressed by address I: (8A+O).H+B) in the vertical mode (see FIG. 5). In other words, 04 of memory chip l has address ((8A+O)・H+B:l
It would be a good idea to give In this case, ny (memory
The position (counting from the top in block M A, B) is 0
It is. Similarly, the bit assigned to 03 of memory cell l
Data P3, 3 is included in the horizontal byte data located at nV=1 in memory blocks MA, B as shown in FIG.
3 has the address ((8A+1)・H) as shown in Figure 5.
+B). Therefore, how to give eight vertical mode memory addresses to each memory chip ICo-07 depends on the bit data P assigned to each memory chip ICo-C7.
It can be seen that it is sufficient to derive the position counted from above nv+nH, that is, ny. In the above example, nH=3, then C4nV=
o, C3: nv == l, +++, C3: ny
=7 holds true. From this example and FIGS. 13 and 14, Co: nv 4-H,=7, C,:ny→-n for C6-C7 of each memory cell l, respectively.
H=6 (mod8), =C7: ny+nH:=0
It can be seen that the correlation (mod 8) holds true. ny
If the value of +nH is unique for each memory chip 1, the memory address given to each memory chip 1 is the n HO value (can be determined by
V==mod8 (d-n)l), and the target memory address ((8A+nv)・I-(+B:
l is obtained. Memory address l' in horizontal mode: (8B+nH)・
V 10A) to 8 memory addresses in vertical mode ((8A 10)・H+B'l~[: (8A +7)
・The operation of the memory circuit of this embodiment in the horizontal mode will be explained in detail, focusing on the operation of the memory address conversion unit 4 that generates H1B"J. Address pointing to any 1-byte data in memory block MA2.3 [(8B10H)・V+A)(
0≦n H≦7) (see FIG. 10) is input to the memory address conversion unit 4, the memory address conversion unit 4 operates as follows. The vertical/horizontal byte (vertical/horizontal byte) register 11 in the memory address conversion unit 4 converts the number of vertical bytes (■) as shown in FIG. The number of horizontal bytes FI is sent to a line 13 and a multiplier line 21 for a multiplier 19, respectively. The memory in which the divider 12 is the dividend. Execute division by the vertical bye l-1:Vl for the address [(8B+n H) ・V+A], put the quotient 18B+n+(] in the quotient line 14, and put the remainder [A] are output to the remainder line 15. The quotient [8B+nI(] is the content of the lower 3 bits [r+,
, ] and the remaining upper bits [B], [n
, 4] are input to the subtracter 17 and simultaneously sent to the memory data conversion unit 9 via the data bus conversion instruction signal line 8. On the other hand, [B] is input to the adder 23 through the negative line I6. The subtracter 17 realizes the derivation of <nv based on the correlation between ny and nH described above. memory cell]
Unique constants d to [n,,] for each cell number C8 to C7 of
"nV" is output to the difference line 18 by subtracting "nV".This difference line 18 is the remainder line 1 of the divider 12.
5 and its contents [8A −+−n v ] are combined with the multiplier 19 by the multiplicand line 20 for the double multiplier 9.
is input. Multiplier 19 multiplicand [3
(Execute multiplication for C+n1be by the horizontal Hyde number [I-1], and obtain the product [(8A-4-nv)・
11] to the product line 22. Next, the adder 23 outputs the content [B] of the upper line 16 of the quotient.
and the contents of the product line 22 [(8A+n v) ・H]
and the result is [(8A+n V) ・H+B]
is output to the sum line 24. The contents of this sum line are sent through eight multiplexers 25 to each memory address bus 2. The memory/data conversion unit 9 receives the code [n,,,](θ≦
n H≧7) using the decoder 31, and
To achieve the correspondence between the memory data line 3 and the CPU data bus 10 according to Figure 4, the buffer enable signal 32 is asserted to one of the eight bidirectional transceiver buffers. do. Through the above operations, memory address [(
8A+nV) ・H1B] (the value of ny is different for each chip), and the memory data line 3 is also connected to CI
) are connected to each bit D7-DO of the U data bus 10, allowing memory access as shown in FIG. As shown in FIGS. 13 and 14, memory cell 1
C3NC7 and each bit D of CPU data bus 10
The correspondence with 7 to Do is data/lotus conversion instruction signal line 8
It is uniquely determined by the above code ny or nH and does not depend on the vertical/horizontal mode. Therefore, the memory/data conversion unit 9 always operates according to the contents of the data/bus conversion instruction signal line 8 regardless of which mode it is in. In this embodiment, as explained above, one memory
64 bits of 8x8 bits in blocks MA, B
Any horizontally continuous 1-byte data (P n
V + O, "nv + 1"', Pny + 7) at address [(8A + nv) ・H + B], and 1 byte data (POnH%
PI+nH+ ”', P71 nH) to address [
(8B0nH).V+A], each can be accessed in one memory cycle. In this case, switching between the vertical mode in which 1-byte data consecutive in the horizontal direction is accessed and the horizontal mode in which 1-byte data consecutive in the vertical direction is accessed is performed using the vertical/horizontal input input to the memory address conversion unit 4. Mode selection signal line 7
By connecting this vertical/horizontal mode selection signal line 7 to the extra CPU address line,
Any one byte of data can be accessed in different modes for each memory cycle. Furthermore, by making the correspondence pattern between C6 to C7 of the memory chip 1 and each bit D7 to Do of the CPU data bus 10 the same in both modes, the memory data conversion unit 9 can be used by the memory address conversion unit 4. Since its operation is determined only by the code on the supplied data bus conversion instruction signal line 8 and does not depend on the current vertical or horizontal mode, the configuration of the memory data conversion unit 9 is simple. In the above embodiment, the memory bus width is 8 bits, but the same effect can be obtained even if the width is expanded to 16 bits. [Effects of the Invention] As explained above, by allocating n bit data constituting one vertical word and one horizontal word in a memory block to n memory chips without duplication, Access to word data with consecutive bits in the sub-scanning line direction, which was conventionally performed by several steps of software, becomes possible in one memory cycle. In addition, it is possible to instantly switch between the vertical mode, in which addresses are continuous in the horizontal (main scanning line) direction, and the horizontal mode, in which addresses are continuous in the vertical (sub-scanning line) direction, using a single signal line.
By connecting to an extra CPU address line, any one word of data can be accessed in different modes every memory cycle. Furthermore, by using a pattern that does not depend on either the vertical or horizontal mode for the correspondence between the memory chip and each bit of the CPU data bus, there is an effect that the configuration of the memory circuit becomes simpler.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a memory circuit according to the present invention. FIG. 2 is a diagram showing memory addresses in vertical mode. FIG. 3 is a diagram showing memory addresses in horizontal mode. FIG. 4 is a diagram showing the concept of memory blocks. FIG. 5 shows memory block MA in vertical mode. 8 is a diagram showing the addresses of 8 byte data of 8, respectively. FIG. 6 shows memory block MA in transverse mode. 8 is a diagram showing the addresses of 8 byte data of 8, respectively. FIG. 7 is a diagram showing the arrangement of 64 bit data in a memory block. FIG. 8 is a diagram showing the bit configuration of 1-byte data in vertical and horizontal modes. FIG. 9 is a diagram showing the configuration of a memory address conversion unit. FIG. 10 is a diagram showing the contents on each signal line in the memory address conversion unit I in the vertical mode. Figure 11 is a diagram showing the contents on each signal line in the memory address conversion unit in horizontal mode. Figure 12 is a diagram showing the contents of the vertical/horizontal byte register. Figure 13 is in vertical mode. data bus and memory
A diagram showing chip correspondence. FIG. 14 is a diagram showing the correspondence between data buses and memory chips in horizontal mode. FIG. 15 is a diagram showing the configuration of the memory/data conversion unit. 1 is a memory chip, 4 (A memory address conversion unit, 7 is a vertical/horizontal mode selection signal line, 8 is a data bus conversion instruction signal line, 9 is a memory data conversion unit, 1] is a vertical/horizontal byte It is a number register.

Claims (3)

[Claims] (1) A memory control device for a memory circuit that uses a memory space two-dimensionally, the n×n generated by dividing the two-dimensional memory space of the memory vertically and horizontally into every certain word (n bits) length. No matter which vertical word or horizontal word data is selected in a memory block consisting of bit data, the n bit data constituting the word data will be stored in each of the n memory chips. A memory control device characterized by having means for allocating without duplication or omission. (2) The memory control device according to claim (1), wherein the memory address given to each of the n memory chips is controlled so that the word data to which access is requested is in the horizontal (main scanning line) direction. The state of the vertical/horizontal mode selection signal line indicating whether bits are continuous (vertical mode) or bits are continuous in the vertical (sub-scanning line) direction (horizontal mode), the preset number of bytes in the horizontal direction, and the vertical means for generating a memory address given to each of the n memory chips from a temporary address given externally for the word data using each constant of the number of bytes in the direction; A memory control device comprising means for determining a connection pattern with n data lines constituting an external data bus. (3) The memory control device according to claim (2), further comprising means for calculating a position within a memory block of the word data to which access is requested, and - A memory characterized in that a connection pattern between a chip and n data lines constituting an external data bus uses a connection pattern that can be determined only by the calculated position regardless of the settings of the vertical/horizontal mode. Control device.