JPH0224047B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electrical delay lines, particularly microminiature delay lines suitable for hybrid circuit applications.

In the market, the standard regular. in. Many electrical delay lines are available in the form of line integrated circuit packages. However, there are no chip-based delay lines suitable for hybrid circuits.

The basic concept of the invention is that at least one pair of series-connected microinductance coils is inserted between films of dielectric material, said material being inserted between films of permalloy or other high magnetic permeability. , one of the latter films extends across the inductance coil,
and provides an electrical delay line forming a strip interrupted at each coil and forming a gap at the central axis of each coil.

It is in accordance with the basic concept that the main object of the invention is achieved, namely to provide a microminiature electrical delay line suitable for hybrid circuit applications.

Another object of the invention is to provide a delay line of the above type which is of simple construction and is economical to manufacture.

The above and other objects and advantages of the present invention include:
The preferred embodiments will become apparent from the detailed description below in conjunction with the accompanying drawings.

As shown in FIG. 5, the delay line of the present invention utilizes an inductive m-type filter, the section of which consists of a pair of series-connected inductance coils 8 (first to fourth
), each with an inductance
L ₁ and between them a mutual inductance M and a branch capacitance C ₁ . The delay line can include any number of such sections as desired, limited only by the tolerable attenuation or loss.

According to the invention, the delay line is made of quartz,
It is constructed and supported by a substrate 10 preferably made of a material suitable for thin film processing of delay line elements as described below, such as glass or other dielectric material. For purposes of the present invention, thin film processing is understood to include processing by vapor deposition techniques as well as printed circuit techniques. Preferred among these is the deposition method described in US Pat. No. 3,785,046. According to this technique, various films are applied by means of a mask, said mask indicating the shape of the areas where the conductive metal and dielectric material deposition is to take place.

As shown, a film 12 of Permalloy, Mumetal, or other suitable high permeability metal is provided over one surface of the substrate 10 and affixed thereto. This film acts as a return path for the magnetic path and as a ground plane for the capacitance of the delay line.
A suitable thickness for this film is approximately 5000 angstroms.

Overlapping and affixed to the entire area of the high permeability metal film 12 is a film 14 of silicon dioxide, silicon nitrite, or other suitable dielectric material. The thickness of this film can vary, as discussed below.

A pair of conductive terminals 16 and 18 are then provided on the dielectric film 14 adjacent one side of the substrate, which are used to connect the delay line to the associated hybrid circuit. If desired, these terminals can extend to the back side of the board 10 to accommodate mounting racks for hybrid circuits on that back side.
The highly permeable metal substrate 12 serves to effectively isolate the hybrid circuit from the delay line.

Next, at least one pair of micro inductance coils 8 are attached and fixed together to the dielectric layer 14. As shown in FIG. 4, ten such inductance coils are provided in two rows spaced apart on the substrate.

Each coil is shown in FIG. 3, each comprising a plurality of superimposed coaxial windings 20 of conductive metal film, with adjacent windings electrically insulated from each other by intervening films 22 of dielectric material. are doing. The innermost and outermost windings extend in opposite directions and laterally into terminators 24 and 25.

Inductance coil 8 forming a delay line
Of all of these, ten are formed simultaneously, as shown in FIG. 4, but spaced in the desired pattern by a properly constructed mask. 6th~
FIG. 15 schematically shows the sequential steps used to form the inductance coil shown in FIG. The first mask is therefore utilized to perform the deposition of the winding segment 30 of the first conductive coil. In the illustrated embodiment, the segment comprises a laterally projecting terminal 24, a portion of which is provided on one of the termination terminals 16, 18, for example on a portion of terminal 18.

Next, with appropriate masking, a quartz film or other suitable dielectric material 32 is deposited across the middle of segment 30 and at the falling terminal of the next conductive winding segment 34 (FIG. 7). Leaving the rising terminals of the segments exposed for conductive connections.

A second treatment of dielectric film 36 is then performed on the trailing edge of conductive segment 34. The mask giving the above processing is the first dielectric processing section 32
The pattern is rotated 180° to expose the lower conductive segment 34.
exposing the rising terminal of the subsequent conductive segment 38
A conductive connection is made to the falling terminal of the terminal. The shape of the latter segment is substantially the same as the shape of the subsequent conductive segment 34, but apparently rotated 180 DEG.

Subsequent dielectric films 40, 44, 48, 52,
56, 60 and 64 and conductive segments 42, 4
6, 50, 54, 58, and 62 are provided alternately (FIGS. 9 to 14), and each inductance coil 8 is The desired number of windings have been completed. 6th
In the embodiment shown in Figures 1-15, a sequence of 41/2 turns of conductive metal is carried out, each winding being electrically separated from each other by a film interposed with dielectric material. There is.

The coil is completed by the addition of a final conductive winding segment 66 and an integrated terminal 26 opposite the starting terminal 24. As shown in Figure 15,
This is achieved by utilizing a mask having an opening of the same shape as that of the mask provided in the first winding segment 30 and connected to the terminal 24 but rotated 180 degrees. In the case where 10 spaced inductance coils are provided, as in the case where the delay line shown in Fig. 4 is employed, the masks referred to when describing the sequences shown in Figs. It contains an opening shaped as required for the same treatment required for the introduction of an inductance coil.

The terminal 26 of the last inductance coil 8 is opposite the first coil, but the second of the pair of terminals 16 and 18, for example the terminal 16 initially provided in the dielectric film 14, as will be seen later. and are provided in electrically conductive engagement with and in an overlapping state. Opposing terminals 24, 26 of adjacent coils 8
is a conductive metal film, such as aluminum,
They are electrically interconnected by links 68 of gold or other suitable metal.

Next, a second film 70 of silicon dioxide, quartz or other suitable dielectric material is applied to interconnect links 68 and adjacent first films of dielectric material.
It is provided not only in the film 14 but also in the series-connected inductance coil 8. This film 70
As shown in FIG. 4, the terminals 16 and 18 are not reached.

Finally, a strip 72 of permalloy or other high permeability metal is provided as a film, preferably about 5000 angstroms thick, overlying the second layer 70 of dielectric material and in series. It extends along the center line of the connection coil 8. This narrow strip of high permeability metal is interrupted at each coil, forming a gap 74 on the centerline with the axis of each coil. It should be noted that the windings of the coil are coaxially stacked on top of each other about the centerline, which is perpendicular to the support surface of the substrate 10.

Permalloy or other high permeability piece extending between the centers of adjacent inductance coils
72 is a high permeability metal film 1 under the coil to provide the necessary mutual inductance M.
We are collaborating with 2. By varying the width of strip 72 and the length of gap 74 at the center of the coil, the desired value of mutual inductance can be obtained. The thickness of dielectric layers 14 and 70 also affects mutual inductance.

Capacitance per section of delay line C ₁
is a high permeability metal substrate surface 1 that includes a region of links 68 and terminals 24, 26 interconnecting opposing terminals of a pair of adjacent inductance coils.
2 and the underside of the inductance coil. This capacitance can be varied by varying the thickness of dielectric layer 14 over the substrate surface and the area of conductive link 68.

The following shows a typical delay line. Assume that the filter inductance L ₁ is 45 nH.
For an m-driven filter with characteristic impedance Z ₀ , the relationship between L ₁ , C ₁ , and Z ₀ is as follows.

Z ₀ =√ L ₁ =0.515L, C ₁ =1.26C, M=0.234L where L and C are the inductance and capacitance per section of the constant K filter.
If the value of Z ₀ is 100 ohms, then C ₁ =1.27L/Z ₀₂ =11.1pf.

If more than one section of the filter is connected directly to obtain the necessary delay time, all inductance coils 8, except at each end of the series network, have an inductance value of 2L ₁ .
Therefore, all inductance coils must have an inductance of 90nb except for the two ends, which each have an inductance of 45nb.

As previously mentioned, magnetic strips 72 and film 12 of permalloy or other high permeability metal provide mutual coupling between two adjacent coils. These things increase the self-inductance of each coil. By properly selecting the width of the magnetic strip 72 and the length of the gap 74, the mutual and self inductances can be varied independently. It is therefore possible to have the same number of windings for all coils for ease of manufacture. magnetic enhancement
By changing the degree of , the termination coil can have half the inductance L ₁ of the other coil 2L ₁ . This is easily achieved,
This is because the terminating coils have only one magnetic piece connecting them.
The two magnetic pieces are not aligned with the other coils.

Assume here that link 68 has the same width as terminals 24 and 26. They are shown narrowly in FIG. 1 for simplicity. The total area of the coil _A1 is
The terminals and links are made of a dielectric layer 14 of silicon dioxide.
The second half winding 30 (FIG. 7), which extends directly across the dielectric layer 14 but is 1.180 square millimeters, or 7.61×10 ^-3 cm ² , and which extends directly across the dielectric layer 14 but does not form the first half winding 30 (FIG. 7) The area of part of the half winding 34 A ₂ is the area
Let ABCDE be 150 square mm, i.e. 0.967×
10 ^-3 cm ² . Therefore, the required capacitance per section is C ₁ =0.08842K (A ₁ /d ₁ +A ₂ /d ₁ +d ₂ ) = 11.1 pf. However, K is the dielectric coefficient of silicon dioxide, and its value is assumed to be 6. d ₁ is the board surface 12
is the thickness of the upper silicon dioxide layer 14, and _d2 is the thickness of the silicon dioxide part between the turns of the coil, 5×10 ^-4
cm2 .

Since A ₂ is smaller than A ₁ and avoiding solving the quadratic equation, the approximate value of d ₁ can be obtained from the following formula: d ₁ = 0.08842KA ₁ + A ₂ /C ₁ = 41.000 Angstroms Therefore, the delay time per section is t ₁ = 1.20 and LC = 1.049 ns.

Therefore, to provide a total delay time of 9 ns, the total number of sections of the delay line would be 9. Fourth
As shown in the figure, this is provided by placing 10 micro inductance coils in two rows of 5 inductors each on a chip, which is approximately 1 cm long and wide. It is 1/4 centimeter.

In view of the foregoing, the present invention provides a microminiaturized delay line of simplified construction for economical manufacture suitable for hybrid circuit applications, in which the mutual impedance per section and It will be appreciated that the value of capacitance can be varied as desired by changing the physical dimensions of the components during manufacturing.

It will be apparent to those skilled in the art that various changes may be made in the size, shape, type, number and arrangement of the components described above without departing from the spirit of the invention.

[Brief explanation of drawings]

1 is an enlarged partial plan view of an electrical delay line embodying features of the present invention; FIG. 2 is a partial cross-sectional view taken from line 2--2 of FIG. 1; and FIG. FIG. 4 is a plan view of a delay line in chip form embodying the features of the invention; FIG. FIGS. 6 to 15 each show a plan view illustrating a good sequence of steps in the formation of the inductance coil shown in FIG. 3; . 8 is a coil, 24 and 26 are terminals, 68 is an interconnection link, 72 is a strip, and 74 is a gap.

Claims (1)

[Claims] 1 a) First film 12 of high magnetic permeability metal
b) a first film 14 of dielectric material disposed on and affixed to a first film of high permeability metal; and c) perpendicularly disposed on and affixed to said first film of dielectric material. a plurality of series-connected micro inductance coils 8; and d) a second film 70 of dielectric material provided and fixed on the inductance coils.
and e) the height of a narrow strip provided on and affixed to the second film of dielectric material and extending along a line connecting the centerlines of each of the series-connected microinductance coils. a second film 72 of magnetically permeable metal with integrated sections interrupted on each coil to form a gap 74 on the centerline of each coil; Ultra-compact electric delay line. 2. Microminiature electric delay line according to claim 1, wherein a substrate 10 of dielectric material is provided and fixed under the first film 12 of high magnetic permeability metal. 3. Each of the plurality of coils 8 is spaced apart in a row and extends in an opposite direction from the coil on the row about a centerline on the gap 74 extending perpendicularly to the plane of the substrate. 3. A microelectric delay line as claimed in claim 2, having opposing terminals 24, 26 that extend, and a conductive metal 68 connecting the opposing terminals of adjacent coils. 4. The micro electric delay line according to claim 2, wherein the substrate 10 is quartz, the high magnetic permeability metal film 12 is permalloy, and the dielectric film 14 is silicon dioxide.