JPH02232986A - Board and manufacture thereof - Google Patents

Board and manufacture thereof

Info

Publication number
JPH02232986A
JPH02232986A JP1052969A JP5296989A JPH02232986A JP H02232986 A JPH02232986 A JP H02232986A JP 1052969 A JP1052969 A JP 1052969A JP 5296989 A JP5296989 A JP 5296989A JP H02232986 A JPH02232986 A JP H02232986A
Authority
JP
Japan
Prior art keywords
opening
chip
hole
board
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1052969A
Other languages
Japanese (ja)
Inventor
Mitsuo Hata
畑 満雄
Keizo Shimokawa
下川 敬三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SANKO DENKI KOGYO KK
Sony Corp
Original Assignee
SANKO DENKI KOGYO KK
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SANKO DENKI KOGYO KK, Sony Corp filed Critical SANKO DENKI KOGYO KK
Priority to JP1052969A priority Critical patent/JPH02232986A/en
Publication of JPH02232986A publication Critical patent/JPH02232986A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections

Abstract

PURPOSE:Not only to decrease a board in total thickness but also to protect a connection part against breakage and disconnection by a method wherein an electronic element is arranged inside an opening formed on a board main body, and the connection terminal of the electronic element is fixed to the inner face of a corresponding through-hole in a lengthwise direction. CONSTITUTION:Two or more through-holes 12 are provided to a base main body 10 nearly along the outline of an IC chip 20. A lengthwise inner face 12a of the through-hole 12 is coated with a plating layer 13, and an opening 14 slightly larger than the chip 20 in size is formed on the base main body 10. The through-holes 12 are cut off along a lengthwise direction to be semicircular in cross section and formed into recesses which serve as parts of end faces 14a of the opening 14. Then, two or more leads 21 of the IC chip 20 are press- fitted into the corresponding through-holes 12 as being brought into contact with the plating layers 13 semicircular in cross section respectively, and the IC chip 20 is housed in the opening 14. Then, the leads 21 are fixed to the plating layers 13 through solder 15 respectively.

Description

【発明の詳細な説明】 1栗上夏1分更 本発明は、基板、特に電子素子を有しかつICメモリカ
ード等の薄型電子部品の製造に使用される基板及びその
製造法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate, particularly a substrate having an electronic element and used for manufacturing thin electronic components such as IC memory cards, and a method for manufacturing the same.

丈来夏皮権 近年. OA (オフィス・オートメーション)機器及
び音響映像(AV)機器等の電子機器との組み合わせで
用いられるICメモリカードは、機器に対応して小型化
、薄型化及び大容量化が進む傾向にある.これに伴い,
プリント配線板に実装される抵抗、コンデンサ、ダイオ
ード、トランジスタ及びICなども小型化及び薄型化さ
れ,一層の高密度実装化が進められている, 一般にプリント配線板の実装方法としてSMT法、リー
ド挿入法,リードレス法、フェイスボンディング法及び
チップオンボード法などが知られている.第9図はSM
T法による実装構造の一例を示す.基板本体1上にはエ
ッチング等の各工程を経て回路パターンのプリント配線
2が形成してあり,ICチップ等の電子素子3を基板本
体1の表面に戟置して,電子素子3の側面から導出され
た複数のりード4をハンダ5によりプリント配線2に接
続している. 通常の実装構造では,基板本体1上に電子素子3を載置
するため、基板本体1の板厚に電子素子3の厚さ寸法が
加わり,基板全体の厚さが増加する.同様に,基板本体
1上のプリント配線2にリード4をハンダ付けして接続
するため、接続部でハンダが盛上がり,プリント配線板
全体の厚さが増大する.従って、前述のような簿型化の
必要なICカードなどへの採用に不利である.かかる不
具合を解消するために、第10図に示す実装構造が提案
されている.この実装構造では,電子素子3の実装部位
に取付孔6を形成し、取付孔6内に電子素子3を基板本
体lの表裏面にほぼ面一となるように配置し、リード4
を折り曲げて基板本体1の表面に形成したプリント配線
2にリード4をハンダ5により接続している.が  し
ようとする課 第10図に示す実装構造では、電子素子3を基板本体1
の取付孔6にほぼ面一で配置することにより、第9@に
示す実装構造での電子素子3による厚さ増加の問題は解
消できる.しかしながら,リード4を折り曲げてその先
端を基板本体1上でプリント配線2にハンダ付けするた
めに,やはり、ハンダの盛り上がりが生じ,プリント配
線板の薄型化に対する基本的な問題を解決できない欠点
がある. 更に、第9図及び第10図に示す従来の実装構造では、
いずれも基板本体1の主面である表裏面に沿って長く延
びるリード4の先端をプリント配線2にハンダ付けしな
ければならないため,複雑なリードフォーミングが要求
される.更に,基板本体1に応力や外力が作用して捩じ
れ又は撓みが生じたとき、リード4にも大きな応力が生
じて、ハンダによる接続部が破断又は剥離する不具合が
ある. そこで、本発明の目的は、上記の欠点を解消して、薄型
化が可能でありかつ変形時に不具合の発生しない基板及
びその製造法を提供することにある. を   るための 本発明による基板は,スルーホールを有する基板本体と
,スルーホールの長さ方向内面を含んで基板本体に形成
された開口部と、接続端子を有しかつ開口部内に配置さ
れた通電素子とからなる.通電素子の接続端子は対応す
るスルーホールの長さ方向内面に固着される.接続端子
はリード又は電極体である.また、通電素子は抵抗,コ
ンデンサ、半導体装It,IC,スイッチ,バッテリ等
の電子素子又は電気素子である. 本発明による基板の製造法は、基板本体に複数のスルー
ホールを形成するスルーホール成形工程と、スルーホー
ルを長さ方向に切断しながら基板本体に開口部を形成す
る開口部成形工程と、開口部内に通電素子を配置しかつ
通電素子の接続端子を対応するスルーホールの長さ方向
内面に固着する組立工程とからなる. 庄一凪 基板本体に形成した開口部内に通電素子を配置し、通電
素子の接続端子を対応するスルーホールの長さ方向内面
に固着するので、基板本体の板厚に通電素子の高さを加
えた基板の全厚さを減少することができる.また,通電
素子の接続端子はスルーホール内で基板本体の主面に垂
直な板厚方向に接続されるので,基板本体に作用する捩
じれ又は撓みに対して強度が増し,接続部の破断又は剥
離を防止できる.更に,接続端子には複雑なフォーミン
グ形状を与える必要がない。
In recent years, the rights to the skin have been increasing. IC memory cards used in combination with electronic equipment such as OA (office automation) equipment and audiovisual (AV) equipment are becoming smaller, thinner, and larger in capacity to match the equipment. Along with this,
Resistors, capacitors, diodes, transistors, ICs, etc. mounted on printed wiring boards are also becoming smaller and thinner, and higher density packaging is progressing.Generally, the SMT method and lead insertion are used as mounting methods for printed wiring boards. known methods include the leadless method, face bonding method, and chip-on-board method. Figure 9 is SM
An example of a mounting structure using the T method is shown. Printed wiring 2 with a circuit pattern is formed on the substrate body 1 through various processes such as etching, and an electronic device 3 such as an IC chip is placed on the surface of the substrate body 1, and the printed wiring 2 is exposed from the side of the electronic device 3. A plurality of derived leads 4 are connected to printed wiring 2 by solder 5. In a normal mounting structure, since the electronic device 3 is placed on the board body 1, the thickness of the electronic device 3 is added to the thickness of the board body 1, increasing the thickness of the entire board. Similarly, since the leads 4 are soldered and connected to the printed wiring 2 on the board body 1, the solder bulges at the connection portion, increasing the thickness of the entire printed wiring board. Therefore, it is disadvantageous for use in IC cards, etc., which require bookkeeping as described above. In order to solve this problem, the mounting structure shown in Figure 10 has been proposed. In this mounting structure, a mounting hole 6 is formed in the mounting part of the electronic element 3, the electronic element 3 is arranged in the mounting hole 6 so as to be almost flush with the front and back surfaces of the board body l, and the leads 4
A lead 4 is connected by solder 5 to a printed wiring 2 formed on the surface of the board body 1 by bending the wire. In the mounting structure shown in Fig. 10, the electronic element 3 is mounted on the board body 1.
By arranging it almost flush with the mounting hole 6, the problem of increased thickness due to the electronic element 3 in the mounting structure shown in No. 9 can be solved. However, since the lead 4 is bent and its tip is soldered to the printed wiring 2 on the board body 1, solder bulges still occur, which has the disadvantage that it cannot solve the basic problem of making the printed wiring board thinner. .. Furthermore, in the conventional mounting structure shown in FIGS. 9 and 10,
In either case, the tips of the leads 4 that extend long along the front and back surfaces, which are the main surfaces of the board body 1, must be soldered to the printed wiring 2, which requires complicated lead forming. Furthermore, when stress or external force acts on the board body 1 and causes it to be twisted or bent, a large stress is also generated in the leads 4, causing the solder connection to break or peel off. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks and provide a substrate that can be made thinner and does not cause defects during deformation, and a method for manufacturing the same. A board according to the present invention for use in the present invention includes a board main body having a through hole, an opening formed in the board main body including the longitudinal inner surface of the through hole, and a connecting terminal disposed within the opening. It consists of a current-carrying element. The connection terminal of the current-carrying element is fixed to the inner surface in the length direction of the corresponding through hole. The connection terminal is a lead or an electrode body. Further, the current-carrying element is an electronic or electric element such as a resistor, a capacitor, a semiconductor device, an IC, a switch, or a battery. The method of manufacturing a substrate according to the present invention includes a through-hole forming process in which a plurality of through holes are formed in a substrate body, an opening forming process in which an opening is formed in the substrate body while cutting the through-holes in the length direction, and an opening The assembly process consists of arranging the current-carrying element within the section and fixing the connection terminal of the current-carrying element to the inner surface in the length direction of the corresponding through-hole. The current-carrying element is placed in the opening formed in the board body, and the connection terminal of the current-carrying element is fixed to the inner surface in the length direction of the corresponding through hole, so the height of the current-carrying element is added to the thickness of the board body. The total thickness of the substrate can be reduced. In addition, since the connection terminals of the current-carrying elements are connected in the through-hole in the board thickness direction perpendicular to the main surface of the board, the strength increases against twisting or bending that acts on the board, and the connection may break or peel. can be prevented. Furthermore, there is no need to provide the connection terminal with a complicated forming shape.

失一N一M 以下,本発明による基板及びその製造法の実施例を第1
図〜第3図に基づいて説明する。
Hereinafter, the first embodiment of the substrate and the method for manufacturing the same according to the present invention will be described.
This will be explained based on FIGS.

プリント配線板としての基板本体10の表面には公知の
製造法によりプリント配線11及びスルーホール12を
含む回路パターンが形成されている.スルーホール12
は公知のエッチング工程及びその他の工程を経てプリン
ト配線11と共に基板本体10に形成され、対応するプ
リント配線11に電気的に接続されている.即ち,スル
ーホール12は、例えば通常のエッチドホイール法又は
アディティブ法などによる銅メッキ処理又はハンダメッ
キ処理が施され、導体被膜として円筒状のメッキ層13
を形成してある.通電素子は、抵抗,コンデンサ、ダイ
オード,トランジスタ又はIC等の電子要素である.I
CはDIP形(Dual inPackage) , 
Q F P形( Q uard F lat P ac
kage ).CC形(Chip Carrier),
 T A B形( T apeAutomated B
onding) ,又はPGA形(PinGrid A
rray)等を含み,挿入タイプ及び表面搭載タイプに
限らず種々の型式のものを使用できる.図示の例では通
電素子としてICチップ20を使用する。ICチップ2
0の樹脂封止体又はバツケージの側端面から複数のリー
ド21が接続端子として導出されている.第3図に示す
ように、基板本体10には開口部14が形成される。開
口部14の一部は、長さ方向に切断されたスルーホール
12の切断面及び長さ方向内面12aによって形成され
る.開口部14内に配置されるICチップ20のリード
21の数に対応する数のスルーホール12が設けられて
いる。スルーホール12は基板本体10の主面10aに
直角な長さ方向内面12aと、長さ方向内面12aに直
角に連続する径方向外面12bとを有する。
A circuit pattern including printed wiring 11 and through holes 12 is formed on the surface of a substrate body 10 as a printed wiring board by a known manufacturing method. Through hole 12
are formed on the substrate body 10 together with the printed wiring 11 through a known etching process and other processes, and are electrically connected to the corresponding printed wiring 11. That is, the through hole 12 is subjected to copper plating or solder plating by, for example, a normal etched wheel method or an additive method, and is coated with a cylindrical plating layer 13 as a conductor coating.
has been formed. The current carrying element is an electronic element such as a resistor, capacitor, diode, transistor or IC. I
C is DIP type (Dual in Package),
Q F P type (Q F P ac
kage). CC type (Chip Carrier),
T A B type (TapeAutomated B
onding), or PGA type (PinGrid A
Various types can be used, including not only insertion type and surface-mounted type. In the illustrated example, an IC chip 20 is used as the current-carrying element. IC chip 2
A plurality of leads 21 are led out as connection terminals from the side end surface of the resin sealing body or baggage. As shown in FIG. 3, an opening 14 is formed in the substrate body 10. As shown in FIG. A portion of the opening 14 is formed by the cut surface of the through hole 12 cut in the length direction and the inner surface 12a in the length direction. A number of through holes 12 are provided corresponding to the number of leads 21 of the IC chip 20 disposed within the opening 14 . The through hole 12 has a longitudinal inner surface 12a perpendicular to the main surface 10a of the substrate body 10, and a radial outer surface 12b continuous to the longitudinal inner surface 12a at right angles.

また、第2図のように、ICチップ20を配置する基板
本体10の開口部14は、基板本体1oの主面10aと
直角な板厚t方向に貫通させて形成される.開口部14
はプレス打抜き加工等で成形され、打抜き加工によって
各スルーホール12は長さ方向に沿ってほぼ半円筒形に
切断される。
Further, as shown in FIG. 2, the opening 14 of the substrate body 10 in which the IC chip 20 is placed is formed to penetrate in the board thickness direction t perpendicular to the principal surface 10a of the substrate body 1o. Opening 14
are formed by a press punching process or the like, and each through hole 12 is cut into a substantially semi-cylindrical shape along the length direction by the punching process.

従って、切断により半円筒形となった複数のメッキ層1
3は間隔を置いて開口部14の端面14aの一部を構成
する.図示の例では,スルーホール12の断面を半円形
断面として示すが、これに限定されず、円弧状、三角形
又は多角形等種々の断面形状に形成することができる。
Therefore, the plurality of plating layers 1 that have become semi-cylindrical by cutting
3 form a part of the end surface 14a of the opening 14 at intervals. In the illustrated example, the cross section of the through hole 12 is shown as a semicircular cross section, but the cross section is not limited to this, and can be formed in various cross sectional shapes such as an arc, a triangle, or a polygon.

本発明の実施例では、第2図に示すように、開口部14
内に配置されるICチップ20は、基板本体10の板厚
tの範囲内、基板本体10の主面10aとほぼ面一又は
基板本体10主面10aから突出して配置することがで
きる.しかし、ICチップを基板本体10の板厚tの範
囲内でICチップ20を収容することが望ましい。実際
には、基板本体10の板厚tにほぼ等しい厚さを有する
ICチップ20を選択することができる.第1図は、I
Cチップ20が開口部14に配置された実装構造を示す
.ICチップ20の樹脂封止体から導出された各リード
21は対応するスルーホール12に固着される.この実
装構造ではりード21のフオーミング形状は特に複雑で
はない。
In an embodiment of the invention, as shown in FIG.
The IC chip 20 disposed within the substrate body 10 can be disposed within the thickness t of the substrate body 10, substantially flush with the principal surface 10a of the substrate body 10, or protruding from the principal surface 10a of the substrate body 10. However, it is desirable to accommodate the IC chip 20 within the range of the board thickness t of the substrate body 10. In reality, an IC chip 20 having a thickness approximately equal to the thickness t of the substrate body 10 can be selected. Figure 1 shows I
A mounting structure in which the C chip 20 is placed in the opening 14 is shown. Each lead 21 led out from the resin molded body of the IC chip 20 is fixed to a corresponding through hole 12. In this mounting structure, the forming shape of the lead 21 is not particularly complicated.

ICチップ20を開口部14内に配置する際に、各リー
ド21は対応するスルーホール12の長さ方向内面12
aに沿って挿入される。各リード21自身の弾力により
スルーホール12の長さ方向内面12aを構成する半円
筒形のメッキ層13に接触する。即ち、各リード部21
は挿入時に内側に変形しつつメッキ層13に接触し、変
形により元の形状に復元しようとする弾性力が発生する
When placing the IC chip 20 in the opening 14, each lead 21 is inserted into the longitudinal inner surface 12 of the corresponding through hole 12.
inserted along a. Due to the elasticity of each lead 21 itself, it comes into contact with the semi-cylindrical plating layer 13 forming the longitudinal inner surface 12a of the through hole 12. That is, each lead portion 21
When inserted, it contacts the plating layer 13 while deforming inwardly, and the deformation generates an elastic force that attempts to restore the original shape.

複数のメッキ層13は開口部14の不導体端面14aに
より互いに分離されかつ電気的にIIAm状態に保持さ
れるので、ICチップ20の複数のり一ド21はメッキ
層13に密着しても、リード21間の通電は阻止される
.しかし、ICチップ20の各リード21は対応するメ
ッキ層13を介して基板本体10上のプリント配1iA
11に電気的に接続される. この状態では、ICチップ20はリード21とメッキ層
13との接触のみで開口部14内に保持されている。次
にハンダ15によりリード21をメッキ層13に固着す
る。これによりICチップ20が開口部14内で位置決
めされる。第1図及び第2図から明らかなように、リー
ド21は基板本体10の板厚tの範囲内でハンダ15に
よりメッキ層13に固着される.従って、リード21及
びハンダ15は基板本体10の主面10aがら外側に突
出せず.ICチップ20のリード21をメッキ層l3に
固゛着することができる.このため、ICチップ20の
主面20aが基板本体10の主面10aの内側に収容さ
れる. 上記の構成により,ほぼ基板本体10の板厚tで基板全
体の厚さを形成することができるから,本発明の基板は
メモリカード,ICカード又は工Dカード等に使用する
基板に最適である.また,外力に基づく曲げ応力,熱応
力又は他の外力が基板本体10に作用して、基板本体1
0に捩じれ又は撓みが生じても,ICチップ20が開口
部14内に配置されておりかつリード21が基板本体1
0に形成された開口部14のメッキ層13に固着されて
いるため、破断力,引張力又は圧縮力が生じてもリード
21には大きな応力が発生しない.このため、リード2
1は撓みなどでリード21の接続部が剥がれ難く,十分
な接続強度を得ることが可能である.また、リード21
は複雑なフォーミング形状で形成されておらず,短い長
さでよく、従来のように基板本体10の主面10aに沿
って長く延びる必要はない. 次に、本発明による第一実施例の基板製造法を説明する
.この製造工程は、 (a)  基板本体10に複数のスルーホール12を形
成するスルーホール成形工程, (b)  スルーホール12を長さ方向に切断しながら
基板本体10に開口部14を形成する開口部成形工程, (c)開口部14内にICチップ20を配置し、ICチ
ップ20のリード21を対応するスルーホール12の壁
面を構成するメッキ層13に固着する組立工程からなる
. 即ち、スルーホール成形工程では,基板本体10に複数
のスルーホールl2がICチップ20のほぼ輪郭に沿う
位置に形成される.各スルーホール12の長さ方向内面
12aはメッキ層13により被覆される.次に,開口部
形成工程では、ICチップ20の縦寸法及び横寸法より
もやや大きい開口部14が基板本体10にプレス加工に
より形成される.スルーホール12のメッキ層13はプ
レス加工前に予め形成されているが,プレス加工後に得
られた各貫通孔の内壁にサブトラクティブ法及びアディ
ティブ法等によりメッキしたり、導電材の充電又はメッ
キ、その他の方法で導体被膜となるメッキ層13を部分
的に形成してもよい.開口部形成工程では、各スルーホ
ール12は長さ方向に沿って半円形断面形状に切断され
る.同時に切断された複数のメッキ層13は互いに間隔
をあけて開口部14の端面14aの一部として凹状に配
置される. 次に、第1図に示すように、組立工程では、ICチップ
20の複数のりード21を対応するスルーホール12の
半円形断面のメッキ層13に接触させつつ圧入し、IC
チップ20を開口部14内に収納する.圧入時に,各リ
ード21はスルーホール12の長さ方向内面12aを構
成するメッキ層13に当接して折り曲げられ、元の形状
に復元しようとする弾性力でメッキ層13の壁面に密着
する.即ち、各リード21が折曲変形によって生じる弾
性作用で、ICチップ20が開口部14に密着しながら
位置決めされる.この後、各リード21をメッキ層13
にハンダ15により固着する。
The plurality of plating layers 13 are separated from each other by the non-conducting end surface 14a of the opening 14 and are electrically maintained in the IIAm state. 21 is blocked. However, each lead 21 of the IC chip 20 is connected to the printed wiring board 1iA on the board body 10 through the corresponding plating layer 13.
It is electrically connected to 11. In this state, the IC chip 20 is held within the opening 14 only by contact between the leads 21 and the plating layer 13. Next, the leads 21 are fixed to the plating layer 13 with solder 15. As a result, the IC chip 20 is positioned within the opening 14. As is clear from FIGS. 1 and 2, the leads 21 are fixed to the plating layer 13 with solder 15 within the thickness t of the board body 10. Therefore, the leads 21 and the solder 15 do not protrude outward from the main surface 10a of the board body 10. The leads 21 of the IC chip 20 can be firmly attached to the plating layer l3. Therefore, the main surface 20a of the IC chip 20 is housed inside the main surface 10a of the substrate body 10. With the above configuration, the thickness of the entire board can be approximately equal to the board thickness t of the board body 10, so the board of the present invention is most suitable for use as a board for memory cards, IC cards, industrial D cards, etc. .. In addition, bending stress, thermal stress, or other external force based on an external force acts on the substrate body 10, causing the substrate body 1 to
Even if the IC chip 20 is placed in the opening 14 and the leads 21 are twisted or bent in the substrate body 1,
Since the lead 21 is fixed to the plating layer 13 of the opening 14 formed at 0, no large stress is generated in the lead 21 even if a breaking force, tensile force, or compressive force is generated. For this reason, lead 2
In case 1, the connection part of the lead 21 is difficult to peel off due to bending, etc., and it is possible to obtain sufficient connection strength. Also, lead 21
is not formed in a complicated forming shape and may have a short length, and does not need to extend long along the main surface 10a of the substrate body 10 as in the conventional case. Next, a method of manufacturing a substrate according to a first embodiment of the present invention will be explained. This manufacturing process includes (a) a through-hole forming process in which a plurality of through-holes 12 are formed in the substrate body 10; (b) an opening process in which an opening 14 is formed in the substrate body 10 while cutting the through-holes 12 in the length direction; (c) an assembly step in which the IC chip 20 is placed in the opening 14 and the leads 21 of the IC chip 20 are fixed to the plating layer 13 forming the wall surface of the corresponding through hole 12; That is, in the through-hole forming process, a plurality of through-holes 12 are formed in the substrate body 10 at positions that substantially follow the outline of the IC chip 20. The longitudinal inner surface 12a of each through hole 12 is covered with a plating layer 13. Next, in the opening forming step, an opening 14 that is slightly larger than the vertical and horizontal dimensions of the IC chip 20 is formed in the substrate body 10 by press working. The plating layer 13 of the through hole 12 is formed in advance before pressing, but the inner wall of each through hole obtained after pressing may be plated by a subtractive method or an additive method, or by charging or plating with a conductive material. The plating layer 13 serving as a conductive film may be partially formed by other methods. In the opening forming step, each through hole 12 is cut into a semicircular cross-sectional shape along its length. A plurality of plated layers 13 cut at the same time are arranged in a concave shape as part of the end surface 14a of the opening 14 with a space between them. Next, in the assembly process, as shown in FIG.
The chip 20 is housed in the opening 14. During press-fitting, each lead 21 contacts the plating layer 13 constituting the longitudinal inner surface 12a of the through hole 12 and is bent, and is brought into close contact with the wall surface of the plating layer 13 by the elastic force that attempts to restore the original shape. That is, the IC chip 20 is positioned in close contact with the opening 14 due to the elastic action generated by the bending deformation of each lead 21. After this, each lead 21 is attached to the plating layer 13.
It is fixed with solder 15.

この状態では、ICチップ20は各リード21及びメッ
キ層13を介して基板本体10上にパターン化されたプ
リント配線11に電気的に接続されている. 次に、本発明の第二実施例を第4図及び第5図について
説明する.これらの図面では,第1図〜第3図に示す個
所と同一の部分には同一符号を付し、説明を省略する.
但し、通電素子としては,抵抗、コンデンサ、ダイオー
ド、トランジスタ又はIC等のリードレス型チップ部品
である.ICはLCC (Laadless Chip
 Carrier)形、PLCC (Plastic 
Loaded Chip Carrier)形,S O
 P ( S wall O utline P ac
kage).形等の表面搭載タイプのものである. この実施例で用いる通電素子は図示の例ではチップIC
30を示す.チップIC30は樹脂封止体の側面に導出
される少なくとも2つの電極体31を有し、チップIC
30を配置する基板本体10の開口部14内に配置され
るチップIC30の電極体31の数に対応する数のスル
ーホール12が開口部14に形成されている。
In this state, the IC chip 20 is electrically connected to the printed wiring 11 patterned on the substrate body 10 via each lead 21 and the plating layer 13. Next, a second embodiment of the present invention will be explained with reference to FIGS. 4 and 5. In these drawings, the same parts as those shown in Figs. 1 to 3 are designated by the same reference numerals, and their explanations will be omitted.
However, the current-carrying elements may be leadless chip components such as resistors, capacitors, diodes, transistors, or ICs. IC is LCC (Ladless Chip
Carrier) type, PLCC (Plastic
Loaded Chip Carrier) type, S O
P (S wall Outline P ac
kage). It is a surface-mounted type. The current-carrying element used in this embodiment is a chip IC in the illustrated example.
30 is shown. The chip IC 30 has at least two electrode bodies 31 led out to the side surface of the resin sealing body.
Through holes 12 are formed in the opening 14 in a number corresponding to the number of electrode bodies 31 of the chip IC 30 disposed in the opening 14 of the substrate body 10 in which the through holes 30 are disposed.

第4図及び第5図は、開口部14に配置されたチップI
C30の各電極体31が対応するスルーホール12に固
着された実装構造を示す.この実装構造では各電極体3
1はそれぞれスルーホール12の径方向内面を構成する
半円筒形のメッキ層13に接触又は近接して対向してい
る.開口部14内にチップIC30を配置すると,電極
体31がメッキ層13に接近又は接触する.チップIC
30の電極体31はハンダ15及びスルーホール12を
介して基板本体10上のプリント配allに電気的に接
続される.しかし、リードレス型のチップIC30の電
極体31は、電極体31を構成する封止樹脂又はセラミ
ック若しくはガラス等のパッケージの表面から殆ど突出
しない。場合によっては電極体31がパッケージの表面
から窪んでいる種々の形式の電子部品を使用することが
できる。図示の実施例では、電極体31はパッケージの
表面から僅かに突出した例を示す。
4 and 5 show the chip I placed in the opening 14.
The mounting structure in which each electrode body 31 of C30 is fixed to the corresponding through hole 12 is shown. In this mounting structure, each electrode body 3
1 are in contact with or close to and face the semi-cylindrical plating layer 13 that constitutes the radial inner surface of the through hole 12, respectively. When the chip IC 30 is placed in the opening 14, the electrode body 31 approaches or contacts the plating layer 13. chip IC
30 electrode bodies 31 are electrically connected to all printed circuit boards on the board body 10 via solder 15 and through holes 12. However, the electrode body 31 of the leadless chip IC 30 hardly protrudes from the surface of the sealing resin, ceramic, glass, or other package that constitutes the electrode body 31. Various types of electronic components can be used, in which case the electrode body 31 is recessed from the surface of the package. In the illustrated embodiment, the electrode body 31 slightly protrudes from the surface of the package.

電極体31をハンダ15によりスルーホール12の長さ
方向内面に固着するとき,半円形断面を有するスルーホ
ール12と電極体31との間にハンダを塗布する。チッ
プIC30の電極体31は、基板本体10の板厚tの範
囲内でハンダ15によりメッキ層13に固着される。従
って、電極体31及びハンダ15が基板本体10の主面
10aから突出又は露出せずに電極体31を固着するこ
とができる.この実装方法によって、チップIC30の
主面20aが基板本体1oの主面10aに対してほぼ面
一又は主面10aの内側で収納することが可能となる。
When fixing the electrode body 31 to the inner surface of the through hole 12 in the longitudinal direction with the solder 15, the solder is applied between the electrode body 31 and the through hole 12 having a semicircular cross section. The electrode body 31 of the chip IC 30 is fixed to the plating layer 13 with solder 15 within the thickness t of the substrate body 10 . Therefore, the electrode body 31 can be fixed without the electrode body 31 and the solder 15 protruding or being exposed from the main surface 10a of the substrate main body 10. This mounting method allows the main surface 20a of the chip IC 30 to be housed substantially flush with the main surface 10a of the substrate body 1o or inside the main surface 10a.

第6図は本発明の第三実施例を示す.この例では,通電
素子としてのチップ部品4oの両端に接続端子41、4
2を形成して、接続端子41、42をハンダによりスル
ーホール12の長さ方向内面12aに接続する。第7図
は通電素子としてのバッテリ5oを使用する例を示す。
Figure 6 shows a third embodiment of the present invention. In this example, connection terminals 41 and 4 are connected to both ends of a chip component 4o as a current-carrying element.
2 is formed, and the connection terminals 41 and 42 are connected to the longitudinal inner surface 12a of the through hole 12 by solder. FIG. 7 shows an example in which a battery 5o is used as the current-carrying element.

バッテリ50の側面とスルーホール12との間にスプリ
ング51を配置して,スプリング51によりバッテリ5
0をスルーホール12に電気的に接続すると共に、バッ
テリ50を開口部14内の一方向に付勢する。
A spring 51 is arranged between the side surface of the battery 50 and the through hole 12, and the spring 51 holds the battery 5.
0 is electrically connected to the through hole 12, and the battery 50 is biased in one direction within the opening 14.

また、バッテリ51の上面にハンダ付け又はスポット溶
接によりL字形の導電部材52の一端を固着し、その他
端をプリント配線11に接続された導電部13aに接続
される.導電部13aは図示の例では開口部14の端面
14aに平坦状に形成されるが,スルーホール12と同
様に半円状に形成してもよい. 更に,第8図は通電素子としてスイッチ60を使用する
例を示す.スイッチ6oは両端に設けられた接続端子6
1.62と、ほぼ中央に設けられた操作ボタン63とを
有する.しかし、スイッチ6oの内部の詳細は図示しな
い.接続端子61、62はハンダ15によりスルーホー
ル12の長さ方向内面12に固着される. 本発明の上記の実施例は種々の変更が可能である.例え
ば、ICチップ20等の通電素子は基板本体10の主面
10aから外側に突出していてもよい.また、基板本体
10の主面10aに絶縁層又は他の基板を積層すること
も可能である.特に、第7図に示す実施例では主面10
aの上に他の基板又はフィルムを積層して、基板又はフ
ィルムに取付けた配線とバッテリ50又は導電部材52
と通電させてもよい。
Further, one end of the L-shaped conductive member 52 is fixed to the upper surface of the battery 51 by soldering or spot welding, and the other end is connected to the conductive part 13a connected to the printed wiring 11. In the illustrated example, the conductive portion 13a is formed in a flat shape on the end surface 14a of the opening 14, but it may be formed in a semicircular shape similarly to the through hole 12. Furthermore, FIG. 8 shows an example in which a switch 60 is used as a current-carrying element. The switch 6o has connection terminals 6 provided at both ends.
1.62 and an operation button 63 provided approximately in the center. However, the internal details of the switch 6o are not shown. The connection terminals 61 and 62 are fixed to the inner surface 12 of the through hole 12 in the longitudinal direction by solder 15. Various modifications can be made to the above-described embodiments of the invention. For example, a current-carrying element such as the IC chip 20 may protrude outward from the main surface 10a of the substrate body 10. It is also possible to laminate an insulating layer or another substrate on the main surface 10a of the substrate body 10. In particular, in the embodiment shown in FIG.
Wires and battery 50 or conductive member 52 attached to the substrate or film by laminating another substrate or film on top of a
You can also energize it.

1JRυ妨展 以上説明したとおり、本発明による基板及び製造法では
、通電素子を基板本体に形成された開口部に配置して、
通電素子から導出された接続端子を対応するスルーホー
ルの長さ方向内面に固着するので、基板の板厚増大が抑
えられ薄型化が可能となり,基板に作用する捩じれ又は
撓みに対する接続部の強度が大きく、接続部の破断又は
剥離を防止できる.従って,例えばメモリカード、IC
カード又はIDカード等の薄型電子部品の一層の薄型化
及び耐久性の向上に大きく貢献することができる.
As explained above, in the substrate and manufacturing method according to the present invention, the current-carrying element is arranged in the opening formed in the substrate body,
Since the connection terminal led out from the current-carrying element is fixed to the inner surface in the length direction of the corresponding through hole, the increase in board thickness is suppressed, making it possible to reduce the thickness of the board, and the strength of the connection part against twisting or bending acting on the board is increased. It is large and can prevent the connection from breaking or peeling. Therefore, for example, memory cards, IC
This can greatly contribute to making thin electronic components such as cards and ID cards even thinner and improving their durability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による基板の斜視図、第2図は本発明に
よる基板の開口部に通電素子を挿入する実装状態を示す
断面図,第3図は本発明による基板の開口部の斜視図、
第4図はチップICを使用する本発明の第二実施例の斜
視図、第5図は第4図に示すチップICを開口部内に挿
入する実装状態を示す断面図、第6図は本発明の第三実
施例を示す斜視図,第7図は本発明の第四実施例を示す
斜視図、第8図は本発明の第五実施例を示す斜視図、第
9図及び第10図はそれぞれ従来の基板の断面図である
. 10・・基板本体、 12・・スルーホール、12a.
.長さ方向内面、 14・・開口部、20..ICチッ
プ(通電素子), 21・・リード(接続端子)、 3
0..チップIC(通電素子)、 31..電極体(接
続端子)、 40..チップ部品(通電素子)、 50
..バッテリ(通電゛素子)、60・・スイッチ(通電
素子).M9 図 第10図
FIG. 1 is a perspective view of a substrate according to the present invention, FIG. 2 is a sectional view showing a mounting state in which a current-carrying element is inserted into an opening in a substrate according to the present invention, and FIG. 3 is a perspective view of an opening in a substrate according to the present invention. ,
FIG. 4 is a perspective view of a second embodiment of the present invention using a chip IC, FIG. 5 is a sectional view showing a mounting state in which the chip IC shown in FIG. 4 is inserted into an opening, and FIG. 7 is a perspective view showing a fourth embodiment of the present invention, FIG. 8 is a perspective view showing a fifth embodiment of the present invention, and FIGS. 9 and 10 are perspective views showing a fifth embodiment of the present invention. Each is a cross-sectional view of a conventional board. 10... Board body, 12... Through hole, 12a.
.. Inner surface in the length direction, 14...opening, 20. .. IC chip (current-carrying element), 21...Lead (connection terminal), 3
0. .. Chip IC (current carrying element), 31. .. Electrode body (connection terminal), 40. .. Chip parts (current-carrying elements), 50
.. .. Battery (current-carrying element), 60... Switch (current-carrying element). M9 Figure 10

Claims (6)

【特許請求の範囲】[Claims] (1)スルーホールを有する基板本体と、上記スルーホ
ールの長さ方向内面を含んで基板本体に形成された開口
部と、接続端子を有しかつ上記開口部内に配置された通
電素子とからなり、上記通電素子の接続端子を対応する
上記スルーホールの長さ方向内面に固着したことを特徴
とする基板。
(1) Consisting of a board body having a through hole, an opening formed in the board body including the longitudinal inner surface of the through hole, and a current-carrying element having a connection terminal and disposed within the opening. . A board, wherein the connection terminal of the current-carrying element is fixed to the inner surface in the length direction of the corresponding through hole.
(2)接続端子はリード又は電極体である請求項(1)
に記載の基板。
(2) Claim (1) wherein the connecting terminal is a lead or an electrode body.
The substrate described in .
(3)通電素子は抵抗、コンデンサ、半導体装置、IC
、スイッチ、バッテリ等の電子素子又は電気素子である
請求項(1)に記載の基板。
(3) Current-carrying elements are resistors, capacitors, semiconductor devices, and ICs.
2. The substrate according to claim 1, which is an electronic device or an electric device such as a switch, a battery, or the like.
(4)基板本体に複数のスルーホールを形成するスルー
ホール成形工程と、スルーホールを長さ方向に切断しな
がら基板本体に開口部を形成する開口部成形工程と、開
口部内に通電素子を配置しかつ通電素子の接続端子を対
応するスルーホールの長さ方向内面に固着する組立工程
とからなる基板の製造法。
(4) A through-hole forming process in which multiple through-holes are formed in the board body, an opening forming process in which an opening is formed in the board body while cutting the through-holes in the length direction, and a current-carrying element is placed within the opening. A method of manufacturing a board, which further comprises an assembly step of fixing a connecting terminal of a current-carrying element to the inner surface in the length direction of a corresponding through hole.
(5)通電素子は抵抗、コンデンサ、半導体装置、IC
、スイッチ、バッテリ等の電子素子又は電気素子である
請求項(4)に記載の基板の製造法。
(5) Current-carrying elements are resistors, capacitors, semiconductor devices, and ICs.
5. The method of manufacturing a substrate according to claim 4, wherein the substrate is an electronic device or an electric device such as a switch, a battery, or the like.
(6)接続電極はリード又は電極体である請求項(4)
に記載の基板の製造法。
(6) Claim (4) wherein the connecting electrode is a lead or an electrode body.
The manufacturing method of the substrate described in .
JP1052969A 1989-03-07 1989-03-07 Board and manufacture thereof Pending JPH02232986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1052969A JPH02232986A (en) 1989-03-07 1989-03-07 Board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1052969A JPH02232986A (en) 1989-03-07 1989-03-07 Board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH02232986A true JPH02232986A (en) 1990-09-14

Family

ID=12929719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1052969A Pending JPH02232986A (en) 1989-03-07 1989-03-07 Board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH02232986A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315032A (en) * 1992-04-01 1993-11-26 Nec Corp Printed circuit board and mounting part therefor
JPH05327168A (en) * 1992-05-15 1993-12-10 Gurafuiko:Kk Printed-wiring board having device soldering defect preventive structure and device having soldering defect preventive structure
JPH08228071A (en) * 1994-11-10 1996-09-03 Vlt Corp Electrical part package
EP0740496A1 (en) * 1995-04-28 1996-10-30 AT&T IPM Corp. Method for fabricating highly conductive vias
WO1997024021A1 (en) * 1995-12-22 1997-07-03 Ibiden Co., Ltd. Substrate for mounting electronic part and process for manufacturing the same
JP2006032415A (en) * 2004-07-12 2006-02-02 Rohm Co Ltd Mount structure and network structure of solid-state electrolytic capacitor on printed circuit board
US11013118B2 (en) 2019-05-23 2021-05-18 Jujube Llc Electronic component mounting structure and method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315032A (en) * 1992-04-01 1993-11-26 Nec Corp Printed circuit board and mounting part therefor
JPH05327168A (en) * 1992-05-15 1993-12-10 Gurafuiko:Kk Printed-wiring board having device soldering defect preventive structure and device having soldering defect preventive structure
US5619791A (en) * 1994-06-30 1997-04-15 Lucent Technologies Inc. Method for fabricating highly conductive vias
JPH08228071A (en) * 1994-11-10 1996-09-03 Vlt Corp Electrical part package
EP0740496A1 (en) * 1995-04-28 1996-10-30 AT&T IPM Corp. Method for fabricating highly conductive vias
WO1997024021A1 (en) * 1995-12-22 1997-07-03 Ibiden Co., Ltd. Substrate for mounting electronic part and process for manufacturing the same
US6201185B1 (en) 1995-12-22 2001-03-13 Ibiden Co., Ltd. Substrate for mounting electronic part having conductive projections and process for manufacturing the same
KR100300624B1 (en) * 1995-12-22 2001-09-29 엔도 마사루 Substrate for mounting electronic part and process for manufacturing the same
JP2006032415A (en) * 2004-07-12 2006-02-02 Rohm Co Ltd Mount structure and network structure of solid-state electrolytic capacitor on printed circuit board
JP4502732B2 (en) * 2004-07-12 2010-07-14 ローム株式会社 Mounting structure and network structure for printed circuit board in solid electrolytic capacitor
US11013118B2 (en) 2019-05-23 2021-05-18 Jujube Llc Electronic component mounting structure and method

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