JPH022293B2 - - Google Patents

Info

Publication number
JPH022293B2
JPH022293B2 JP59116057A JP11605784A JPH022293B2 JP H022293 B2 JPH022293 B2 JP H022293B2 JP 59116057 A JP59116057 A JP 59116057A JP 11605784 A JP11605784 A JP 11605784A JP H022293 B2 JPH022293 B2 JP H022293B2
Authority
JP
Japan
Prior art keywords
plating
lead
lead frame
tie bar
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59116057A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60260142A (ja
Inventor
Mitsuhiro Myazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP11605784A priority Critical patent/JPS60260142A/ja
Publication of JPS60260142A publication Critical patent/JPS60260142A/ja
Publication of JPH022293B2 publication Critical patent/JPH022293B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP11605784A 1984-06-06 1984-06-06 リ−ドフレ−ム Granted JPS60260142A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11605784A JPS60260142A (ja) 1984-06-06 1984-06-06 リ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11605784A JPS60260142A (ja) 1984-06-06 1984-06-06 リ−ドフレ−ム

Publications (2)

Publication Number Publication Date
JPS60260142A JPS60260142A (ja) 1985-12-23
JPH022293B2 true JPH022293B2 (enrdf_load_html_response) 1990-01-17

Family

ID=14677633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11605784A Granted JPS60260142A (ja) 1984-06-06 1984-06-06 リ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS60260142A (enrdf_load_html_response)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5082802A (en) * 1985-11-12 1992-01-21 Texas Instruments Incorporated Method of making a memory device by packaging two integrated circuit dies in one package
US5014112A (en) * 1985-11-12 1991-05-07 Texas Instruments Incorporated Semiconductor integrated circuit device having mirror image circuit bars bonded on opposite sides of a lead frame
JPH0777252B2 (ja) * 1986-12-11 1995-08-16 三菱電機株式会社 半導体装置用リ−ドフレ−ム
JP3553461B2 (ja) 2000-04-27 2004-08-11 新光電気工業株式会社 部分めっき装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5223270A (en) * 1975-08-15 1977-02-22 Dainippon Printing Co Ltd Method of manufacturing lead frames for semiconductors
JPS53125938A (en) * 1977-04-12 1978-11-02 Toshiba Corp Plating method of lead frame
JPS5891650A (ja) * 1981-11-26 1983-05-31 Toshiba Corp 半導体装置
JPS58127356A (ja) * 1982-01-26 1983-07-29 Nippon Texas Instr Kk 半導体集積回路の樹脂封止法およびそのために用いるリ−ドフレ−ム

Also Published As

Publication number Publication date
JPS60260142A (ja) 1985-12-23

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