JPH02226971A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To realize a synthesis pattern with simple scanning by providing a magnification processing circuit using a memory able to store a video signal by one screen so as to form a magnified picture and a synthesis processing circuit to output a synthesized picture between the output of the magnification processing circuit and the input video signal. CONSTITUTION:When a magnified picture is desired to be observed singly and an operating section 48 gives a command of it, a system controller 47 controls a selection signal generator 49 to throw a switch 44 always to the position of an output side of a switch 43 thereby giving a selection control signal SP. Moreover, a timing controller 46 is used to give a timing to a write address reset of a FIFO 41. Thus, the magnified picture signal from the switch 43 is outputted from an output terminal OUT. Furthermore, when the operation section 48 commands the synthesis of the magnified picture and the original input screen, the video signal obtained from the switch 44 results in an original input screen for the right half of the screen and the left half to be the magnified pattern in which the middle portion of the screen of the right half is magnified by twice.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing circuit, and particularly to a video signal processing circuit having a function of enlarging an image.

[Prior Art] Conventionally, video signal enlargement processing has been generally achieved by using a random access memory (RAM) and controlling its read address according to a predetermined program.

Hereinafter, such a conventional method will be briefly explained.

Now, a description will be given of converting a video signal representing an original image as shown in FIG. 6(A) into a video signal representing an enlarged image as shown in FIG. 6(B). FIG. 7 is a diagram showing an example of the configuration of a conventional enlargement processing circuit, and FIGS. 8(A) and 8(B) are diagrams for explaining the operation of the circuit shown in FIG.

In FIG. 7, an analog video signal input manually from an input terminal 20 is converted into a digital signal by an AD converter 21 and supplied to a field memory 22 consisting of a RAM.

At this time, the write address corresponds to each pixel of the human image in a one-to-one correspondence with the storage area in the field memory 22, as shown in FIG. 3(A). When reading these images, only the pixels (3-3, 3-4, 4-3, 4-4) located in the center of the screen are horizontally moved as shown in Figure 8 (B). By repeating reading twice in the scanning direction and twice in the vertical scanning direction, for a total of four degrees, a video signal corresponding to an image enlarged twice was obtained. Such address sterilization is performed by the address control circuit 24 according to the timing signal from the timing control signal generation circuit 25.
This was done in synchronization with the /A converter 23. In the figure, W indicates a write address control signal, and R indicates a read address control signal. As a result, an analog video signal corresponding to the desired enlarged image is obtained from the D/A converter 23.

Furthermore, the present applicant has previously applied for a method of realizing the above-mentioned enlargement process using a so-called first-in first-out memory (Japanese Patent Application No. 17413/1983).

[Problems to be Solved by the Invention] By the way, although it is possible to view a screen subjected to such enlargement processing on its own, a very interesting screen can be obtained by combining it with other screens.

However, the reality is that such processing is generally installed in business equipment but not in home consumer equipment. The reason for this is that in order to perform the above processing, a processing circuit for image enlargement, a processing circuit for images to be synthesized, an instruction circuit for determining the center of image enlargement, an instruction circuit for determining an image synthesis pattern during synthesis, etc. is necessary,
This is because the scale of the circuit becomes enormous, and furthermore, it is extremely troublesome to give the above-mentioned complicated instructions at home.

Against this background, it is an object of the present invention to provide a video signal processing circuit that can realize various combination patterns by simple scanning when an enlarged image is combined with another image.

[Means for Solving the Problems] For the above purpose, the video signal processing circuit of the present invention includes an enlargement processing circuit capable of forming an enlarged image using a memory capable of storing a video signal for one screen; a composition processing circuit for outputting a composite image of the output of the enlargement processing circuit and an input video signal; selection means for selecting a composition pattern of the composition processing circuit; and selection means for selecting a composition pattern of the composition processing circuit; The configuration includes switching means for switching the writing or reading timing to the memory.

[Operation] By configuring as described above, the operator can set the ideal center of enlargement for the enlarged image by simply selecting the combination pattern of the enlarged image and other images, and there is no need to perform any complicated operations. There will be no need for it.

[Example〕 An embodiment of the present invention will be described below.

FIG. 1 is a block diagram showing the configuration of a video signal processing circuit as an embodiment of the present invention, and an input terminal indicated by IN in the figure is supplied with an analog video signal such as a reproduction signal from a VTR. This human-powered analog video signal is A/D
A converter 40 digitizes it into multiple bits. In FIG. 1, it is assumed that all components from the A/D converter 40 to a D/A converter 50, which will be described later, handle multi-bit digital signals.

With the processing circuit shown in FIG. 1, the selection signal generator 49, which operates according to control data from the system controller 47 when no enlargement processing is performed, outputs an output control signal SP to always connect the switch 44 to the A side. As a result, the same analog video signal as the analog video signal input from the input terminal IN is output from the output terminal OUT.

Next, image enlargement processing according to the present invention will be described.

Figures 2 and 3 show F in Figure 1 when the image is enlarged.
FIG. 4 is a timing chart used to explain the processing timing of I FO4 1, and FIG. 4 is a schematic diagram used to explain this processing. FIG. 2 shows the vertical scanning timing. FIG. It shows.

The synchronization separation circuit 45 extracts a vertical synchronization signal (VD) and a horizontal synchronization signal (
These synchronization signals VD and HD determine the timing of each control signal output by the timing controller 46.

In Fig. 2, VD is a vertical synchronization signal, and WE is F
The IFO 41 has a write enable signal, RE is a read enable signal, WR is a write reset signal, RR is a read reset signal, WD is write data, and RD is read data.

Now, assume that the area a on the screen shown in FIG. 4 is to be enlarged. As shown in FIG. 2, the write enable signal WE is at a high level (H) that enables writing during the period in which the video signals corresponding to the areas a and 2 in FIG. 4 are manually input.
), and at a low level that disables writing during other periods (
L), and only the video signals corresponding to the areas A and S are written into the FIFO 41. To explain more precisely, the write enable signal WE changes to H at the timing when the point indicated by R in FIG. 4 is being scanned, and changes to L after the repair field. The timing at which this write enable signal WE changes to H is the timing shown by R in FIGS. 2 and 3. On the other hand, the write reset signal WR is a signal that has a pulse during a certain period (in the example of FIG. 2, in synchronization with the vertical synchronization signal) when the write enable signal is applied once every two fields, and the write clock WC to the FIFO 41 The frequency is such that data can be written in all areas of the FIFO 41, which is one field memory, in one field period. Therefore, P I
Assuming that the FO41 has a capacity that corresponds to one field of video signal, the video signal data corresponding to the areas A and A will be written for two fields in a two-field period. Note that the numerical values in the schematic diagram of the write data WD in FIG. 2 are field numbers, and the shaded area indicates a period in which there is no write data.
Also, a, b in the schematic diagram of write data WD in FIG.
, c indicate video signal data corresponding to areas a, b, and c in FIG. 2, respectively.

On the other hand, the read clock RC at this time is the write clock W.
It is set to the frequency reported by C, and the time axis is expanded by 2 times for 2 fields during the 2-field period, and FI FO
41. Since the frequency of the read clock RC is equal to the frequency of the write clock WC, the read enable signal RE must be H for twice the period of the write enable signal WE.
It becomes H in all periods except the vertical synchronization period. The read reset signal RR is a signal that has a pulse once every two fields in synchronization with the vertical synchronization signal at the timing to operate the upper left end in FIG.
Read data RD as schematically shown in D is obtained. That is, in the read data from the FIFO 41, only the upper left corner of FIG. and corresponding video signals alternately.

CP in FIG. 2 indicates a control pulse supplied from the timing controller 46 to the switch 43,
As shown in the figure, during the horizontal scanning period when the video signal data corresponding to area a is output from the FIFO 41,
During the horizontal scanning period in which video signal data corresponding to one area is output, L is raised. The switch 43 is connected to the IHDL 42 side when the control pulse CP is L, and connected to the other side when it is H. Therefore, from this switch 43, one horizontal scan of video signal data corresponding to area a is repeatedly output twice. Therefore, the video signal outputted from this switch 43 is a video signal showing an image obtained by enlarging the image of area a in FIG. 4 twice.

Next, various forms of outputting the enlarged image obtained as described above will be explained using FIGS. When the system controller 47 instructs this in the section 48, the system controller 47 controls the selection signal generator 49 and outputs the selection control signal SP to always connect the switch 44 to the output side of the switch 43. The write address of the FIFO 41 is reset at the timing R shown in Figures 2 to 4.As a result, the image within the dotted line in the left diagram of Figure 5(A) corresponds to the image enlarged to fill the entire screen. A video signal is obtained from the switch 43, and an enlarged image signal output from the switch 43 is output from the output terminal 0LIT.

Next, a case will be described in which a composite screen of an enlarged image and a human image is obtained. For example, as shown in FIG. 5(B), an explanation will be given of the operation when the operation section 48 constituting the selection means of the present invention is used to specify that the right half of the screen should be the enlarged screen and the left half should be the original input screen. .

The system controller 47 also controls a selection signal generator 49 constituting the selection means of the present invention, and sends a selection control signal s.
p and switch 44 to A/D during the first half of each horizontal scanning period.
The latter half of the converter 40 side is connected to the output side of the switch 43. Further, the timing controller 46 constituting the switching means of the present invention resets the write address of the FIFO 41 at the timing when the input video signal scans the portion indicated by R in the left diagram of FIG. 5(B). Close. As a result, the switch 43 obtains a video signal corresponding to an image in which the images connected within the dotted line in the left diagram of FIG. 5(A) are enlarged to cover the entire screen. Therefore, as shown in the right diagram of FIG. 5(B), the video signal obtained from the switch 44 is such that the left half of the screen is the human-powered screen, and the right half is the central part of the left half of the screen, which is doubled. It becomes an enlarged screen that is enlarged to 100%, making it an extremely practical and interesting screen.

Furthermore, even when the operation unit 48 is used to specify that the left half of the screen should be the enlarged screen and the right half should be the original input screen, as shown in FIG. The control signal SP is applied to connect the switch 44 to the output 40 side of the switch 43 during the first half of each horizontal scanning period, and to the output side of the A/D converter 40 during the second half of each horizontal scanning period.
The write address reset of O41 is performed at the timing when the manual video signal scans the portion indicated by R in the left diagram of FIG. 5(C). This similarly causes switch 4
In the video signal obtained from 4, the right half of the screen is the original input screen, and the left half is an enlarged screen that doubles the center of the right half of the screen, making it an extremely practical and interesting screen.

These image compositions stop writing to PIFO41,
The same process can be performed even if the enlarged image is a still image.

According to the video signal processing device of the embodiment as described above, enlarged images of various patterns and original images can be effectively synthesized with extremely simple operations, and furthermore, FIFO can be used in the circuit configuration. Because it has a simple circuit configuration, it is extremely effective in incorporating such advanced processing into a single consumer device.

Note that the present invention is not limited to the specific circuit configuration shown in FIG.
The same can be achieved with a configuration using a random access memory as shown in the figure. In this case, the generation pattern of RAM write or read addresses should be stored in a look-up table such as a read-only memory (ROM), and the pattern generated from this ROM should be switched according to the selected composite pattern. A similar effect can be obtained. Furthermore, when RAM is used in this way, it will be possible to handle even more complex combination patterns.

[Effects of the Invention] As described above, according to the video signal processing circuit of the present invention, various synthesis patterns can be realized by simple scanning when an enlarged image is synthesized with another image.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a video signal processing circuit as an embodiment of the present invention, and FIGS. 2 and 3 are timing charts for explaining the operation of each part of the circuit in FIG. 1 during enlargement processing, respectively. , Fig. 4 is a schematic diagram for explaining the enlargement process by the processing circuit shown in Fig. 1, and Figs. 5 (A), (B), and (C) show the enlarged image and original image that are omitted by the circuit shown in Fig. 1. 6(A) and 6(B) are diagrams illustrating an example of a conventional enlarged image. FIG. 7 is a block diagram illustrating an example of the configuration of a processing circuit that performs conventional image enlargement. , FIGS. 8(A) and 8(B) are schematic diagrams for explaining the operation of the circuit shown in FIG. 7. In the figure, IN is an input terminal, OUT is an output terminal, 41 is a FIFO with a capacity for 1 field, and 42 is an IHDL. 4344 is a switch, 45 is a synchronous separation circuit, 46 is a timing controller, 47 is a system controller, and 48 is an operation unit. ㅅp い亨2-庨3I￥1 小魁4-Kiyae1口(δ)

Claims (2)

[Claims] (1) An enlargement processing circuit capable of forming an enlarged image using a memory capable of storing a video signal for one screen, and a composition processing circuit for outputting a composite image of the output of the enlargement processing circuit and the input video signal. A video signal processing circuit comprising: a selection means for selecting a synthesis pattern of the synthesis processing circuit; and a switching means for switching writing or reading timing to a memory in the enlargement processing circuit in accordance with the selection means. (2) The video signal according to claim (1), wherein the memory is constituted by a first-in first-out memory, and the switching means controls a write reset timing of the first-in first-out memory. processing circuit.