JPH02214225A - Encoder circuit - Google Patents

Encoder circuit

Info

Publication number
JPH02214225A
JPH02214225A JP3396089A JP3396089A JPH02214225A JP H02214225 A JPH02214225 A JP H02214225A JP 3396089 A JP3396089 A JP 3396089A JP 3396089 A JP3396089 A JP 3396089A JP H02214225 A JPH02214225 A JP H02214225A
Authority
JP
Japan
Prior art keywords
bit
bit lines
input
encoder circuit
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3396089A
Other languages
Japanese (ja)
Inventor
Akio Tanii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3396089A priority Critical patent/JPH02214225A/en
Publication of JPH02214225A publication Critical patent/JPH02214225A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up an encoder circuit with many bit number by providing two bit lines per one bit and a switch switching a bit line to an input section and an output section respectively.
CONSTITUTION: When an input signal enters any of bases 3-5 at the time of changing over the input to an encoder circuit (through state) with the entire system clock and switches 8, 9 are thrown to the position of upper terminals, coding is implemented by using bit lines 6b, 7b and a level of the bit lines 6b, 7b is changed in response to the inputting. Then the level of the bit lines 6b, 7b is confirmed when the input (at latch) to the circuit is confirmed by using the entire system clock and a low-order bit is outputted from the bit line 6b and a high-order bit is outputted from the bit line 7b. When the clock is switched to attain the through-state again, the switches 8, 9 are changed over and coding is applied similarly by using the bit lines 6a and 7a. The bit lines 6, 7 are used alternately in such a way to attain processing at a double speed.
COPYRIGHT: (C)1990,JPO&Japio
JP3396089A 1989-02-14 1989-02-14 Encoder circuit Pending JPH02214225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3396089A JPH02214225A (en) 1989-02-14 1989-02-14 Encoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3396089A JPH02214225A (en) 1989-02-14 1989-02-14 Encoder circuit

Publications (1)

Publication Number Publication Date
JPH02214225A true JPH02214225A (en) 1990-08-27

Family

ID=12401059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3396089A Pending JPH02214225A (en) 1989-02-14 1989-02-14 Encoder circuit

Country Status (1)

Country Link
JP (1) JPH02214225A (en)

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