JPH02206831A - Full adder circuit - Google Patents

Full adder circuit

Info

Publication number
JPH02206831A
JPH02206831A JP2793589A JP2793589A JPH02206831A JP H02206831 A JPH02206831 A JP H02206831A JP 2793589 A JP2793589 A JP 2793589A JP 2793589 A JP2793589 A JP 2793589A JP H02206831 A JPH02206831 A JP H02206831A
Authority
JP
Japan
Prior art keywords
circuit
signal
level
carry
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2793589A
Other languages
Japanese (ja)
Inventor
Ikuo Yasui
Eiichi Teraoka
Yukihiko Shimazu
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2793589A priority Critical patent/JPH02206831A/en
Publication of JPH02206831A publication Critical patent/JPH02206831A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a full adder circuit which can operate at a higher speed by detecting the current difference or the voltage difference of a complementary output signal and outputting the signal of an addition result in sense amplifier circuits.
CONSTITUTION: The XOR signal and the XNOR signal of input signals are outputted in a first and second logical circuits 21 and 22. A first level assurance circuit 31 assures the levels of the signals outputted from the circuit 21 to a power potential or an earth potential and gives them to the circuit 22. A second level assurance circuit 32 assures the levels of the signals outputted from the circuit 22 to the power potential or the earth potential and gives them to the input of the first sense amplifier circuit 41. Transmission gate circuits 51 and 52 cause the input signals to pass or interrupt them in accordance with the levels of the output signals of the circuit 21. A carry signal deletion circuit 61 controls the level of a carry input signal which the circuit 51 has caused to pass. A carry signal generation circuit 62 controls the level of the complementary signal of the carry input signal which the circuit 52 has caused to pass in accordance with the level of the signal A or B. The second sense amplifier circuit 42 outputs a carry output signal CO and the complementary signal, the inverse of CO from output terminals Y and the inverse of Y.
COPYRIGHT: (C)1990,JPO&Japio
JP2793589A 1989-02-07 1989-02-07 Full adder circuit Pending JPH02206831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2793589A JPH02206831A (en) 1989-02-07 1989-02-07 Full adder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2793589A JPH02206831A (en) 1989-02-07 1989-02-07 Full adder circuit

Publications (1)

Publication Number Publication Date
JPH02206831A true JPH02206831A (en) 1990-08-16

Family

ID=12234753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2793589A Pending JPH02206831A (en) 1989-02-07 1989-02-07 Full adder circuit

Country Status (1)

Country Link
JP (1) JPH02206831A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0646860A1 (en) * 1993-10-04 1995-04-05 Kabushiki Kaisha Toshiba Full adder circuit
JPH07200257A (en) * 1993-12-28 1995-08-04 Nec Corp Nmos path transistor circuit and adder

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0646860A1 (en) * 1993-10-04 1995-04-05 Kabushiki Kaisha Toshiba Full adder circuit
US5596520A (en) * 1993-10-04 1997-01-21 Kabushiki Kaisha Toshiba CMOS full adder circuit with pair of carry signal lines
JPH07200257A (en) * 1993-12-28 1995-08-04 Nec Corp Nmos path transistor circuit and adder

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