JPH0220154B2 - - Google Patents
Info
- Publication number
- JPH0220154B2 JPH0220154B2 JP18943982A JP18943982A JPH0220154B2 JP H0220154 B2 JPH0220154 B2 JP H0220154B2 JP 18943982 A JP18943982 A JP 18943982A JP 18943982 A JP18943982 A JP 18943982A JP H0220154 B2 JPH0220154 B2 JP H0220154B2
- Authority
- JP
- Japan
- Prior art keywords
- enamel
- glass frit
- printed circuit
- circuit board
- electrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 19
- 210000003298 dental enamel Anatomy 0.000 claims description 18
- 239000011521 glass Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000002950 deficient Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910000831 Steel Inorganic materials 0.000 description 7
- 230000007547 defect Effects 0.000 description 7
- 239000010959 steel Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000004070 electrodeposition Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000004534 enameling Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000002659 electrodeposit Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、ホーロープリント基板の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a hollow printed circuit board.
ホーロープリント基板は、第1図に示すよう
に、鋼板1などの上に例えば厚さ0.13ミリメート
ル(mm)程度のホーローエナメル2を焼成したも
ので、放熱性や機械的強度の点で優れた特性を持
つものである。特に放熱特性をを生かすために
は、ホーローエナメル2を薄くすることが好まし
い。しかしながら第2図に示すように、ホーロー
エナメル2の内部に気泡3やピンホール4が発生
していたりすると、絶縁耐圧が著しく低下すると
いう問題が生ずる。この絶縁耐圧低下を防止する
一方法として、ホーロー掛けを数回に分けて施す
ことが考えられるが、厚さが増加して放熱性が損
われ易くなるばかりでなく、工程数が増えてコス
ト上昇を招き易い。 As shown in Figure 1, the enameled printed circuit board is made by firing enameled enamel 2 with a thickness of about 0.13 millimeters (mm) on top of a steel plate 1, etc., and has excellent properties in terms of heat dissipation and mechanical strength. It is something that has. In particular, in order to take advantage of its heat dissipation properties, it is preferable to make the enamel enamel 2 thin. However, as shown in FIG. 2, if bubbles 3 or pinholes 4 are generated inside the enamel enamel 2, a problem arises in that the dielectric strength voltage is significantly lowered. One way to prevent this drop in dielectric strength voltage is to apply the enamel in several steps, but this not only increases the thickness and easily impairs heat dissipation, but also increases the number of steps and increases costs. easy to invite.
すなわち、従来におけるホーロープリント基板
の製造は、第3図に示す工程例のように行なわれ
る。 That is, the conventional manufacturing of hollow printed circuit boards is carried out as shown in the process example shown in FIG.
S1:鋼板を必要な大きさに加工する工程。S1: Process of processing steel plates into the required size.
S2:鋼板に「バリ」取り、脱脂、酸洗いなどの
前処理を施す工程。S2: A process in which the steel plate undergoes pretreatment such as removing burrs, degreasing, and pickling.
S3:ガラスフリツト(ホーローエナメル構成材)
を鋼板に電着、湿式スプレー、静電法などに
より塗装する工程。S3: Glass frit (enamel component)
The process of painting steel plates using electrodeposition, wet spraying, electrostatic methods, etc.
S4:塗装されたガラスフリツトの溶液分を乾燥
させる工程。S4: Drying the painted glass frit solution.
S5:ガラスフリツトを例えば800〜850℃で溶融
し、ホーローエナメルを鋼板に密着焼成する
工程。S5: A process in which glass frit is melted at, for example, 800 to 850°C, and the enamel is baked in close contact with the steel plate.
などである。したがつて、ホーロー掛けを数回に
分けて施す場合は、第3図のS3ないしS5の工程
が繰り返され、そのたびに加熱と冷却を必要とす
るなど、作業時間が長くなるなどの問題を生ずる
ものである。etc. Therefore, when enameling is applied in several steps, the steps S3 to S5 in Figure 3 are repeated, which requires heating and cooling each time, which increases the work time. It is something that occurs.
本発明は前記事情に基づいてなされたもので、
その目的とするところは、ピンホールなどの存在
によつて生ずる電気的欠陥部を強制的に絶縁破壊
して、この部分にガラスフリツトを電着塗装して
焼成することにより、均一なホーローエナメル層
を有するとともに絶縁耐圧に優れたホーロープリ
ント基板を提供することにある。 The present invention was made based on the above circumstances, and
The purpose is to forcibly break down the electrical defects caused by the presence of pinholes, etc., and then electrodeposit glass frit on these areas and bake them to create a uniform enamel layer. It is an object of the present invention to provide a hollow printed circuit board having a high dielectric strength and excellent dielectric strength.
以下、本発明を第4図に示す一実施例に基づい
て説明する。これらの工程において、S1ないし
S5は従来の製造工程と同一である。続いて、S6
以下の工程を辿る。 The present invention will be explained below based on an embodiment shown in FIG. In these processes, S1 to
S5 is the same as the conventional manufacturing process. Next, S6
Follow the steps below.
S6:S5で完成したホーロープリント基板に、絶
縁耐圧試験時の基準電圧(例えばAC50Hz
1000V)以上の電圧を印加して、第2図に示
したような電気的欠陥部を絶縁破壊し、ホー
ローエナメル層を貫通して鋼板と外気とを強
制的に連通させる(絶縁破壊時の短絡電流に
より穴を明ける)工程。S6: Apply the reference voltage (for example, AC50Hz) during the dielectric strength test to the hollow printed circuit board completed in S5.
Applying a voltage of 1000 V or more causes dielectric breakdown at the electrical defect as shown in Figure 2, penetrating the enamel enamel layer and forcibly communicating the steel plate with the outside air (short circuit at dielectric breakdown). (drilling holes using electric current) process.
S7:電圧印加により電気的破壊が生じない
(「NO」である。)場合は供試品を異常のな
いものとし、一方、絶縁破壊が発生した場合
は、S8以下の工程を付加するために、絶縁
破壊の有無を判定する工程。S7: If electrical breakdown does not occur due to voltage application (“NO”), the sample is considered to be normal. On the other hand, if dielectric breakdown occurs, the process from S8 onwards is added. , the process of determining the presence or absence of dielectric breakdown.
S8:第5図Aに示すように、外気と連通状態に
ある欠陥部に電着塗装法によりガラスフリツ
ト5を電着させ充填する工程。この工程にお
いては、基本的にS3と同一種のガラスフリ
ツトが使用される。また、電着塗装の際には
絶縁性の悪い部分、すなわち電気的欠陥部に
電気力線が集中するため、ガラスフリツト5
の充填は効果的に実施される。S8: As shown in FIG. 5A, a step of electrodepositing glass frit 5 by electrodeposition coating method to fill the defective part which is in communication with the outside air. In this step, basically the same type of glass frit as S3 is used. In addition, during electrodeposition coating, lines of electric force concentrate in areas with poor insulation, that is, electrical defects, so the glass frit 5
The filling is carried out effectively.
S9:前工程において電着塗装されたガラスフリ
ツトの余剰分を溶媒液で洗うなどすることに
より、取り除く工程。S9: A process in which the excess of the glass frit that was electrodeposited in the previous process is removed by washing with a solvent solution.
S10:ガラスフリツトの溶液分を乾燥させる工
程。S10: Drying the glass frit solution.
S11:ガラスフリツトを例えば800〜850℃で溶融
し、充填ホーローエナメル6として他のホー
ローエナメル2と第5図Bに示すように一体
化する工程。S11: A step of melting the glass frit at, for example, 800 to 850°C and integrating it with another enamel 2 as a filled enamel 6 as shown in FIG. 5B.
なお、ここまでの工程において、S10および
S11はS4およびS5と同一で施設の相互利用、また
は兼用が可能であり、S3とS8とを同一施設で処
理することも可能である。 In addition, in the process up to this point, S10 and
S11 is the same as S4 and S5, and the facilities can be mutually used or used together, and it is also possible to process S3 and S8 in the same facility.
また、S8においてガラスフリツトの組成がS3
と同一種であるとしたが電気的に塗装または封孔
可能であれば、他の塗料、含浸剤とすることも可
能である。 In addition, in S8, the composition of the glass frit is S3.
Although it is said that it is the same type as , it is also possible to use other paints and impregnation agents as long as they can be electrically painted or sealed.
しかして本発明によれば、
ホーローエナメル層に電気的欠陥がある場
合、強制的に電気破壊して穴を明け、この部分
の充填ホーローエナメルと一体化されるから、
電気絶縁性に優れた均一なホーロープリント基
板を製造することができる。 However, according to the present invention, if there is an electrical defect in the enamel layer, the hole is forcibly destroyed by electric breakdown, and the hole is integrated with the enamel filling in this part.
A uniform hollow printed circuit board with excellent electrical insulation can be manufactured.
電気的欠陥を対象として充填ホーローエナメ
ル層のホーロー掛けが行なわれるから、ホーロ
ーエナメル層の厚さの増加を防止して、放熱性
を一定とすることができる。 Since the filled enamel enamel layer is enameled to target electrical defects, it is possible to prevent the thickness of the enamel layer from increasing and to maintain constant heat dissipation.
電気的欠陥部へのガラスフリツトの充填は、
電気的力線が集中する電着塗装によつて行なわ
れるから作業効率を向上させることができる。 Filling electrical defects with glass frit
Since it is carried out by electrodeposition coating in which electric lines of force are concentrated, work efficiency can be improved.
などの効果を奏するものである。It has the following effects.
第1図はホーロープリント基板の構造例を示す
縦断面図、第2図は第1図の鎖線で示す部分を
拡大した電気的欠陥の説明図、第3図は従来の製
造方法の工程例を示すフローチヤート、第4図は
本発明を実施するための工程例を示すフローチヤ
ート、第5図A,Bは第4図の工程例におけるホ
ーロー掛けの状態を示す説明図である。
1……鋼板、2……ホーローエナメル、3……
気泡、4……ピンホール、5……ガラスフリツ
ト、6……充填ホーローエナメル。
Fig. 1 is a vertical cross-sectional view showing an example of the structure of a hollow printed circuit board, Fig. 2 is an explanatory diagram of an electrical defect, which is an enlarged view of the part indicated by the chain line in Fig. 1, and Fig. 3 is an example of the process of the conventional manufacturing method. FIG. 4 is a flowchart showing a process example for carrying out the present invention, and FIGS. 5A and 5B are explanatory views showing the state of enameling in the process example of FIG. 4. 1... Steel plate, 2... Enamel, 3...
Air bubbles, 4...pinholes, 5...glass frits, 6...filled enamel enamel.
Claims (1)
する工程と、破壊された欠陥部にガラスフリツト
を電着塗装する工程と、電着塗装されたガラスフ
リツトを加熱焼成する工程とを含有するホーロー
プリント基板の製造方法。1. A process for producing an enamel printed circuit board, which includes the steps of electrically destroying defective parts of the enamel enamel layer, electrodepositing glass frit on the destroyed defective parts, and heating and baking the electrodeposited glass frit. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18943982A JPS5978595A (en) | 1982-10-28 | 1982-10-28 | Method of producing porcelain printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18943982A JPS5978595A (en) | 1982-10-28 | 1982-10-28 | Method of producing porcelain printed board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5978595A JPS5978595A (en) | 1984-05-07 |
JPH0220154B2 true JPH0220154B2 (en) | 1990-05-08 |
Family
ID=16241262
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18943982A Granted JPS5978595A (en) | 1982-10-28 | 1982-10-28 | Method of producing porcelain printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5978595A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013042181A (en) * | 2005-12-12 | 2013-02-28 | Tdk Corp | Method of manufacturing a capacitor |
-
1982
- 1982-10-28 JP JP18943982A patent/JPS5978595A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5978595A (en) | 1984-05-07 |
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