JPH02194373A - Method for displaying simulation result - Google Patents

Method for displaying simulation result

Info

Publication number
JPH02194373A
JPH02194373A JP1013647A JP1364789A JPH02194373A JP H02194373 A JPH02194373 A JP H02194373A JP 1013647 A JP1013647 A JP 1013647A JP 1364789 A JP1364789 A JP 1364789A JP H02194373 A JPH02194373 A JP H02194373A
Authority
JP
Japan
Prior art keywords
circuit diagram
simulation
information
simulation results
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1013647A
Other languages
Japanese (ja)
Inventor
Atsushi Ogura
尾倉　淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1013647A priority Critical patent/JPH02194373A/en
Publication of JPH02194373A publication Critical patent/JPH02194373A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make simulation results and circuit diagrams correspond to each other instantaneously and to obtain the results of all signal lines of a circuit line at a time by simulating pieces of information on respective parts of the circuit line by a computer and combining the results with the circuit diagrams. CONSTITUTION:Pieces of information from storage devices 1 and 2 stored with circuit diagram information and input information of simulation are inputted to the computer 3 to perform simulation. A storage device 4 for output information is stored with the simulation results of all the signal line of the circuit diagrams. Further, the circuit diagram information from the device 1 and the simulation result from the device 4 are combined by a display controller 5 to display the circuit diagram and simulation results on a graphic display 6 at a time.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、回路図のシミュレーション結果を表示する方
法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for displaying simulation results of circuit diagrams.

従来の技術 従来、回路図のシミュレーション結果を表示する方法と
して、各部の波形をグラフィック装置に出力したり、プ
ロッターに出力していた。第３図に従来例としての回路
図（イ）と波形図（ロ）を示す。回路図（イ）において
、１８はインバータ、１９はＮｏｒでゲート、２０はＮ
ΔＮ　Ｉ）グー］・、２１はインバータをボす。BACKGROUND ART Conventionally, as a method for displaying simulation results of circuit diagrams, the waveforms of various parts were output to a graphic device or to a plotter. FIG. 3 shows a circuit diagram (a) and a waveform diagram (b) as a conventional example. In the circuit diagram (A), 18 is an inverter, 19 is a Nor gate, and 20 is an N
ΔN I) Goo]・, 21 blows the inverter.

この回路図（イ）に、入力化シー；２２．２３．２４を
入力したシミュレーション結果を、波形図（ロ）に示し
ている。２２〜２４は入力信号の波形図、２５〜２８は
出力信号の波形図を示す。The waveform diagram (B) shows the simulation results obtained by inputting the input signals C; 22, 23, and 24 into this circuit diagram (A). 22 to 24 are waveform diagrams of input signals, and 25 to 28 are waveform diagrams of output signals.

発明が解決しようとする課題 しかしながら、上記のような従来の方法では、回路図（
イ）と波形図（ロ）とが別々に表示されているので、両
者の対応に手間がかかったり、回で表示する波形の数に
限度があるため、回路図の全ての信号線のシミュレーシ
ョン結果を一度に得られないという問題点があった。Problems to be Solved by the Invention However, in the conventional method as described above, the circuit diagram (
Since the waveform diagram (a) and waveform diagram (b) are displayed separately, it takes time and effort to correspond to both, and there is a limit to the number of waveforms that can be displayed at a time. There was a problem in that it was not possible to obtain the following at once.

本発明の目的は、−に記従来の問題点を解決するもので
、シミュレーション結果と回路図とを即座に対応させ、
また、−度に回路図の全ての信じ線のシミュレーション
結果を得ることのできる方法を提供しようとするもので
ある。An object of the present invention is to solve the problems of the conventional art described in - by immediately correlating simulation results and circuit diagrams;
It is also an attempt to provide a method that can obtain simulation results for all belief lines in a circuit diagram at once.

課題を解決するための手段 本発明は」１記目的を達成するために、回路図情報の記
憶装置とシミュレーションの人力情報の記憶装置からの
信号を計算機に入力して回路図の全ての信じ線のシミュ
レーション結果を出力情報の記憶装置に記憶させ、表示
制御装置を介して指定する時刻のシミュレーション結果
を回路図と結合してグラフィックディスプレー」二に表
示するようにしたシミュレーション結果の表示方法とし
た。Means for Solving the Problems In order to achieve the object described in item 1, the present invention inputs signals from a circuit diagram information storage device and a simulation human input information storage device into a computer to input all the belief lines of the circuit diagram. The simulation result is stored in an output information storage device, and the simulation result at a specified time is combined with a circuit diagram via a display control device and displayed on a graphic display.

作用 」−記のように本発明では回路線の各部の情報をａ１算
機に入力して、シミュレーションさせ、このシミュレー
ション結果と回路図とを結合させることにより、両者の
対応が即座に可能となり、回路図の全ての信号線のシミ
ュレーション結果を一度に得ることができるようになっ
た。In the present invention, information on each part of the circuit line is input into the A1 computer and simulated, and by combining the simulation results with the circuit diagram, it is possible to immediately correspond to the circuit diagram. Simulation results for all signal lines in a circuit diagram can now be obtained at once.

実施例 以下、本発明の詳細な説明する。第１図において、ｌは
回路図情報を記憶している記憶装置、２はシミュレーシ
ョンの入力情報を記憶している記憶装を五で、これら記
憶装置１．２からの情報な言−１算機３に入力して、シ
ミュレーションをさせる。４は出力情報の記憶装置で、
１ｉｉＪ記回路図の全ての信号線のシミュレーション結
果を記憶させる。さらに、記憶装置１からの回路図情報
と記憶装置４からのシミュレーション結果を表示制御装
置５で結合させて、回路図とシミュレーション結果を一
度に同時にグラフィックディスプレー６に表示するよう
にした。EXAMPLES The present invention will be described in detail below. In FIG. 1, l is a storage device that stores circuit diagram information, 2 is a storage device that stores simulation input information, and 5 is a storage device that stores simulation input information. 3 and run the simulation. 4 is a storage device for output information;
1ii Store the simulation results of all signal lines in the circuit diagram. Furthermore, the circuit diagram information from the storage device 1 and the simulation results from the storage device 4 are combined by the display control device 5, so that the circuit diagram and the simulation results are simultaneously displayed on the graphic display 6.

第２図はグラフィックディスプレー６による表示例を示
すもので、ディジタル回路と、その指定した時刻の全信
号線のシミュレーション結果とを同時に表示している。FIG. 2 shows an example of a display on the graphic display 6, in which a digital circuit and the simulation results of all signal lines at a specified time are displayed simultaneously.

７はインバータ、８はＮ。7 is an inverter, 8 is N.

Ｒゲート、９はＮＡＮＤゲート、１０はインバータであ
り、１１〜１７は各部の信号線を示す。9 is a NAND gate, 10 is an inverter, and 11 to 17 are signal lines of each part.

信号Ｆｊ＋ｌ＋、１２．１５．１７はシミュレーション
結果がハイレベルであるので、太線として表示し、同様
に信号線１３、Ｉ４．１６はシミュレーション結果がロ
ーレベルであるので細線として表示している。Signals Fj+l+ and 12.15.17 are displayed as thick lines because their simulation results are at a high level, and similarly, signal lines 13 and I4.16 are displayed as thin lines because their simulation results are at a low level.

本実施例で示したシミュレーション結果の表示方法をと
れば、回路図」二の全ての信号線のハイレベル、ローレ
ベルが即座に且つ一度に得ることができる。By using the simulation result display method shown in this embodiment, the high level and low level of all the signal lines in circuit diagram 2 can be obtained instantly and at once.

発明の効果 本発明は」二記のような表示方法を用いることにより、
シミュレーション結果の情報を回路図に付加して表示さ
れ、回路図の信号線とシミュレーション結果との対応が
即座にとれ、また−度に全ての信号線のシミュレーショ
ン結果を得ることができるようになった。Effects of the Invention The present invention uses the display method as described in 2.
Simulation result information is added to the circuit diagram and displayed, allowing immediate correspondence between signal lines in the circuit diagram and simulation results, and also making it possible to obtain simulation results for all signal lines at once. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明方法を実行する構成図、第２図は本発明
によるシミュレーション結果の表示図、第３図（イ）、
（ロ）は従来例の表示図で、（イ）は回路図、（ロ）は
波形図である。 ｌ、２．４・・・記憶装置　　３・・・計算機５・・・
表示制御装置 ６・・・グラフィックデイスプレFig. 1 is a block diagram for executing the method of the present invention, Fig. 2 is a display diagram of simulation results according to the present invention, Fig. 3 (a),
(B) is a display diagram of a conventional example, (A) is a circuit diagram, and (B) is a waveform diagram. l, 2.4...Storage device 3...Computer 5...
Display control device 6...Graphic display

Claims (1)

【特許請求の範囲】[Claims] （１）回路図情報の記憶装置とシミュレーションの入力
情報の記憶装置からの信号を計算機に入力して回路図の
全ての信号線のシミュレーション結果を出力情報の記憶
装置に記憶させ、表示制御装置を介して指定する時刻の
シミュレーション結果を回路図と結合してグラフィック
ディスプレー上に表示するようにしたことを特徴とする
シミュレーション結果の表示方法。(1) Input the signals from the circuit diagram information storage device and the simulation input information storage device into the computer, store the simulation results of all signal lines of the circuit diagram in the output information storage device, and start the display control device. A method for displaying simulation results, characterized in that the simulation results at a time specified through the interface are combined with a circuit diagram and displayed on a graphic display.
JP1013647A 1989-01-23 1989-01-23 Method for displaying simulation result Pending JPH02194373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1013647A JPH02194373A (en) 1989-01-23 1989-01-23 Method for displaying simulation result

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1013647A JPH02194373A (en) 1989-01-23 1989-01-23 Method for displaying simulation result

Publications (1)

Publication Number Publication Date
JPH02194373A true JPH02194373A (en) 1990-07-31

Family

ID=11839022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1013647A Pending JPH02194373A (en) 1989-01-23 1989-01-23 Method for displaying simulation result

Country Status (1)

Country Link
JP (1) JPH02194373A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0498430A (en) * 1990-08-10 1992-03-31 Sony Tektronix Corp Simulator for electric circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0498430A (en) * 1990-08-10 1992-03-31 Sony Tektronix Corp Simulator for electric circuit

Similar Documents

Publication Publication Date Title
JPH02194373A (en) Method for displaying simulation result
JPS5576406A (en) Operation monitor control board
JPH0520464A (en) Display element selection/display device
JPS63157185A (en) Plant noise simulator
JPS5831192Y2 (en) Display device for information processing equipment
JPH01253666A (en) Tester for lsi containing arithmetic circuit
JPS62177637A (en) Display system for simulation result
JP3110326B2 (en) Verification test pattern design equipment
JP2969746B2 (en) Grid display method
JPS58224371A (en) Plant operation training simulator
JPS62137665A (en) Circuit diagram generating device
JPS63128389A (en) Time constant processing system for training simulator
JPH01230088A (en) Training simulator
JPS5739475A (en) Digital computer
JPS5790712A (en) Information processor
JPS61282878A (en) Plant simulator
JPS63250765A (en) Display system simultaneous with simulation execution
JPS57132026A (en) Simulation signal generator
JPS62236069A (en) Sentence processor
JPH05233745A (en) Simulation result display device for asic
JPS6051903A (en) Generating method of process control program
JPH03136172A (en) System and device for processing input of time chart
JPS62280794A (en) Control of character display
JPS63104076A (en) Instructor aid for training simulator
JPH02234185A (en) Training assisting device