JPH02185797A - Address decoder - Google Patents

Abstract

PURPOSE:To decrease the power consumption by using a small number of level shifting circuits by providing (n) pieces of pre-decoders, (n) pieces of first level shifting circuits groups, an intermediate decoder, a second level shifting circuit group and a main decoder. CONSTITUTION:In the case of having comparatively small logical amplitude, (n) pieces of pre-decoders PD1 - PD4 for decoding (n) pieces of address signal parts for constituting an address signal, respectively have a NOR type logic circuit constitution using a bipolar transistor, therefore, those (n) pieces of pre-decoders PD1 - PD4 respond satisfactorily to (n) pieces of address signal parts for constituting an address signal, respectively, and they are decoded, respectively. Also, since a main decoder MD has a NAND type logic circuit constitution using a bipolar transistor, in the main decoder MD, only small power consumption is accompanied at the time of its operation.

Description

[Detailed description of the invention]

[Industrial Application Field 1] The present invention relates to an address decoder. 2. Description of the Related Art Conventionally, an address decoder as described below with reference to FIG. 11 has been proposed. That is, the address signal A of the first to (i+j10k) bits. The address signal from the 1-bit address signal 9 section A1 consisting of the first to i-th bits constituting the address signal is processed by the decoding output group B1 of 21 bits consisting of the first to second bits. Pre-decoder PD1 decodes to decode output, and address signal A of the first to (i+j+k)th bits. The (i+1)-th to (i+
one-bit address signal part A consisting of bits j)
2 address signals from <2+1) to <2'
+2j) bits, and a predecoder PD2 for decoding into a decode output from a decode output group B2 of 2j bits. In this case, predecoders PD and PD2 are
Although the explanation is omitted, as shown in the ffT2 diagram, a NOR type logic circuit configuration using bipolar transistors is shown. In addition, throughout the figures, Q is an npn type bipolar transistor, Q' is a pnp type bipolar transistor, R is a resistor, C is an argument element, M is a ρ channel type MIS field effect transistor, and M' is an n channel type. Type Mis-
ffi field effect transistor, )" is a constant current source, DI is a diode, VC is a high potential power supply terminal (for example, OVA, VE
V8 indicates a low potential power supply terminal (for example, -5, 2V), and V8 indicates an intermediate potential power supply terminal (for example, -3, OV). In addition, the address signal A of the first to (i+j10k)th bits
. The (i+j+1)th to (i+j+k)th composing
The address signal color by the address signal part A3 of bits from the th bit, (i+j+1) to m(i+j
+k)? Similarly, the positive address signal part F of the bits consisting of the fS-th bit and the (i+j+i)-th to (i-th
It has an address signal section output circuit K that outputs a negated address signal section F' of (i+j10k)-th bits. As shown in FIG. 12, each address signal output circuit constituting this address signal portion output circuit K is an N type transistor using bipolar transistors. It has an R-type logic circuit configuration. Furthermore, the decode output 8 has level-shifted the decode outputs from the two decode output groups B1 and B2- from the predecoder PD and PD2 to the lower voltage side.
It has two level shift circuits IsH and Sn2 that level shift the decoded outputs by 1B' and B. In this case, the level shift circuit group SH1 has two level shift circuits 81 to S, (p=2), and these are emitter floor circuits using bipolar transistors, as shown in FIG. It has a configuration. Further, the level shift circuit group SH2 includes 2J level shift 1-circuits Sp+1 to Sq (q=2+2"),
As shown in FIG. 14, they use an emitter floor circuit configuration using bipolar transistors, similar to the level shift circuits 81-S. However, level shift circuits SP+, ~S of level shift circuit group SH2
Although q depends on the decode output group 82' outputted from them, the level is shifted to a lower potential side compared to the decode output. Also, a kv:I level shift circuit S for level shifting the address signal of the affirmative address signal NSF consisting of bits from the address signal section output circuit K to the lower voltage side.
There are level shift circuits SK' for shifting the address signal of the negative address signal section F' consisting of k bits to the lower voltage side. Each of these level shift circuits SK and SK' is
As shown in FIG. 15, it has an emitter floor circuit configuration using bipolar transistors. Furthermore, it consists of a decode output from a decode output group B' consisting of 21 bits from the level shift circuit group SH, and a decode output from a decode output group 82' consisting of 2j bits from the level shift circuit group SH2. The decoded output is outputted from the k level shift circuits SK and 2xk level shift circuits selected in a predetermined order from among the 2xk level shift circuits composing the k level shift circuits SK'. 1st to 2nd K (=a) main decoders MD each decodes into a decode output by a decode output group 01 to Ca (2k = a) consisting of (2' + 2j) bits using the address signals; ~MD, and right. In this case, each of main decoders MO, -MD has a NAND type logic circuit configuration using bipolar transistors, as shown in FIG. Further, a decode output group of 2i+j+ bits as a whole consisting of decode output groups C1 to Ca outputted from main decoders MD1 to MD, respectively, is an address signal A. As a decode output of 21+j+ inverters 11 configured using MIS field effect transistors,
1b (b = 2''+k). The above is the configuration of the conventionally proposed address decoder. According to the address decoder having such a configuration, the address signal A. If it has a relatively small logic amplitude,
Since predecoders PD1 and PD2 have a NOR type logic circuit configuration using bipolar 1-transistors, these predecoders PD1 and PD2 receive address signal A. It responds well to address signal sections A and A2, respectively. Further, since the address signal section output circuit also has a NOR type logic circuit configuration using bipolar transistors, the address signal A is output. It responds well to the address signal section A3. Further, each of main decoders MD1 to MD8 has N
Since it has an AND type logic circuit configuration, the main decoder M
Each of D1-MDa involves low power consumption during its operation. Furthermore, each of main decoders MD1 to MDa has N
Even if it has an AND type logic circuit configuration, its main decoders MD1 to MD. Then, the decode outputs from the decode output groups B and B2 from the predecoders PD and PD2 are level-shifted to the decode outputs from the decode output groups B1' and B', which are level-shifted by the level shift circuit groups SH1 and SH2, respectively. Since the main decoders MD1 to MDa respond well, the main decoders MD1 to MD output decode outputs from the decode output groups 01 to C3 having relatively large logic amplitudes. Therefore, in the case of the conventional address decoder shown in FIG. 11, the (j+j+k) bit address signal A has a relatively small logic amplitude. can be decoded into a decode output consisting of bits of 2j''j+l(, which has a relatively large logic amplitude as a whole. Therefore, the decode output group can be decoded by using M■S field effect transistors. It is possible to supply the configured inverter group and operate the inverter group favorably.

[Problems to be Solved by the Invention] However, in the case of the conventional address decoder described above in FIG. 11, in addition to the predecoders PDI and PD2, 2'll! Main decoders MD1 to M of J
D, (a=2k), and therefore,
Decoders other than predecoders PD1 and PD2 consume large amounts of power. Furthermore, in the case of the conventional address decoder described above in FIG. 11, the address signal A of (i + j + k) bits is decoded into a 2 bit decode output, 21 level shift circuits 81 to Sp (p=2) in level shift circuit group St-+, and level shift circuit group 5
2J shift circuits in 1-1 must be used, and therefore, the level shift circuit groups SH and SH
2 involves relatively large power consumption. From the above, the conventional address decoder described above in FIG. 11 has the drawbacks of having to use a large number of level shift circuits and consuming a large amount of power. , it is an object of the present invention to propose a new address decoder that does not have the above-mentioned drawbacks. [Means for Solving the Problems] The address decoder according to the present invention has the following features: n predecoders each having a NOR type logic circuit configuration using bipolar transistors, each decoding the address signal from the address signal section of (an integer of a group of n first level shift circuits using bipolar transistors that level shift the decoded outputs;
A NAND type logic circuit configuration using bipolar transistors is used to decode the decode output from the (n-1) III decode output group from the (n-1) first level shift circuit group in the level shift circuit group. an intermediate decoder having: (1) a second level shift circuit group for level-shifting the decode output by the decode output group from the intermediate decoder; (2) a decode output by the decode output group from the second level shift circuit group; It has a NAND type logic circuit configuration using bipolar transistors, which decodes the decode output consisting of the decode output from the decode output group from the remaining Ml level shift circuit group among the n first level shift circuit groups. It has a main decoder.

[Action/effect]

When the address signal has a relatively small logic amplitude, as in the case of the conventional address decoder described above in FIG. Since the predecoder has a NOR type logic circuit configuration using bipolar transistors, these n predecoders constitute an address signal in the same way as in the case of the predecoder of the conventional address decoder described above in FIG. n address signal portions, respectively, and decodes them respectively. Further, since the main decoder has a NAND type logic circuit configuration using bipolar transistors, like each of the main decoders in the conventional address decoder described above in FIG.
As in each of the main decoders of the conventional address decoders described above in Figure 1, their operation involves low power consumption. Further, the main decoder has a NAND type logic circuit configuration, and the main decoder has a decode output from a group of decode outputs from an intermediate decoder and a group of decode outputs from one predecoder among n predecoders. The decode output consisting of the decode output from the intermediate decoder and the decode output from the decode output group from one of the predecoders of n1llil is supplied to the second decode output.
Since the main decoder is level-shifted and supplied to the decode output from the decode output group that has been level-shifted by one level shift circuit group among the level shift circuit group of n Wil's level shift circuit groups and n Wil's level shift circuit groups, As in each case of the main decoder of the conventional address decoder described above in FIG. 11, it responds well. Further, the main decoder has a NAND type logic circuit configuration, and the NAND type logic circuit configuration has a decode output from a decode output group from a second level shift circuit group and a first level shift circuit of nl[lil. 1 in the group
Since it is sufficient to configure the NAND logic between the decode outputs from the decode output group from the first level shift circuit group and the decode output from the decode output group from the first level shift circuit group, a voltage drop is generated in the bipolar transistors forming the NAND type logic circuit. Also outputs a decode output by a decode output group having a relatively large logic amplitude. Furthermore, since the intermediate decoder also has a NAND type logic circuit configuration like each of the main decoders of the conventional address decoder described above in FIG. 11 and similarly to the main decoder, during its operation, Like each of the main decoders of the conventional address decoder and like the main decoder, it involves low power consumption. Furthermore, even if the intermediate decoder has a NAND type logic circuit configuration, the intermediate decoder has decode outputs from (n-1) decode output groups from the l-111 predecoders among the n predecoders. is level-shifted and supplied to the decode output from the decode output group, which is level-shifted by the (n-1) level shift circuit groups among the n first level shift circuit groups, so that the intermediate decoder , responds well as well as each of the main decoders of the conventional address decoder described above in FIG. From the above, according to the address decoder according to the present invention, as in the case of the conventional address decoder described above in FIG. 11, an address signal having a relatively small logic amplitude is decoded into a decode output having a large logic amplitude. can be done. However, for the address decoder according to the invention,
Since the address signal can be decoded by using only two decoders, an intermediate decoder and a main decoder in addition to the n predecoders, the decoder excluding the n predecoders can be used as shown in FIG. Incurs only 2/2 the power fi cost of the conventional address decoder described above. In addition, in the case of the address decoder according to the present invention, one intermediate decoder at the subsequent stage for (n-1) predecoders among the n predecoders, and one intermediate decode after the (n-1) predecoders among the n predecoders; and one intermediate decoder and one main decoder at the subsequent stage thereof, so that address signals of the same number of bits are
To decode to the decoded output with the same number of bits, the first
It is necessary to use a significantly smaller number of level shift circuits than in the case of the conventional address decoder described above in FIG.
Compared to the conventional address decoder described above in the figure, the power consumption is significantly lower. Therefore, in the case of the address decoder according to the present invention, the eleventh
It is necessary to use a significantly smaller number of level shift circuits than in the case of the conventional address decoder described above in FIG. It only involves consumption.

【Example】

Next, an embodiment of the address decoder according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 11 are designated by the same reference numerals, and detailed description thereof will be omitted. The artless decoder according to the present invention shown in FIG. 1 has the following configuration. That is, the first to (i+j++I) address signals A. n (n is an integer of 3 or more; however, hereinafter, for simplicity, it will be referred to as n-4) address signals of A1, A2, A3, and A4 constituting the address signal portions A1, A2, A3, and A4. n-4) predecoder P
D, PD, PD3 and PD4. In this case, the predecoder PD1 decodes the first to M(i+j+
+I) bit address signal A. The address signal from the address signal part A1 of one bit consisting of the first to i-th bits constituting the
Of the 21 bits consisting of the 21st bit (2' bits, only one bit is "1" (high potential) in binary display, and all the others are "OJ (low N rank)" in binary display. )
is decoded into a decode output group B1. Further, the predecoder PD2 has the first to the (+l to +J+)
) bit address signal A. The (++1st
) to the (i+j)th bit, the address signal from the three-bit address signal section A2 is
2j bits consisting of ~(2i + 2j) bits (out of 2j bits, only one bit is "1" (high potential) in binary representation, all others are binary representation [OJ (
It is decoded into the decode output group B2 (which takes a low potential). Further, the predecoder PD3 receives the address signal A of the first to (+I to i+j+) bits. The j address signal portion A3 of the (i+j+1)th to (i+j+k)th bits constituting the
2' + 2j + 2k) bits (out of 2' bits, only one bit has a binary representation - (
"rlJ (high potential), all others are "0" in binary display (
It is decoded into the decode output group B3 (which takes a low potential). Further, the predecoder PD4 has the first to (i-1-j
10k+1) bit address signal A. One-bit address signal part A consisting of bits from the (i+j++1) to (i+j++1) bits constituting the
4, the (2' + 2j + 2 + 1) to (2i + 2
j +2k +21 ) bits (among 2fL bits, only one bit is "1" (high potential) in binary representation, and all the others are "0" (
It is decoded to the decode output group B4 (which takes a low potential). The predecoder PD-PD4 is an N-type predecoder using bipolar transistors, as shown in FIG. 2 and similar to the conventional address decoder described above in FIG. 11, although a detailed explanation will be omitted. It has an R-type logic circuit configuration. In addition, pre-decoders PD 1PD2, PD3 and PD
Four decoded output groups B1B2, B and B4 from
There are four level shift circuit groups SH1SH1SH3 and SH4 for level-shifting the decoded outputs of the respective decoded outputs to the lower potential side. Level shift circuit group S! 1 has 21 level shift circuits that level shift the 21-bit decode output group B1 consisting of the first and second bits from the predecoder PD to the decode output group B'. Although detailed explanation is omitted, as shown in FIG. 3, it has a configuration in which it is connected to a common constant current circuit H,
Therefore, only one of the two level shift circuits operates. However, the output terminals of the two level shift circuits of the level shift circuit group 5t-11 are derived as shown by solid lines in FIG. Level-shifting group B2 to decode output group 82'2
j level shift circuits, which similarly have a configuration in which they are connected to a common constant current circuit H, as shown in FIG. 3, although detailed explanation is omitted.
Therefore, only 2j level shift circuits operate. However, in FIG. 3, the 2j level shift circuits of the level shift circuit group S12 have a value lower by one diode drop voltage than the decode output group 81' output from the level shift circuit SH1, as shown by the chain line in FIG. An output terminal for outputting a level-shifted decode output group B' is derived. Further, the level shift circuit group SH3 receives signals from <2 +2 +1)-th to (<2 +2 +1)-th
It has two level shift circuits that level shift the decode output group 83 of 2 bits consisting of 2' + 2j + 2k) bits to the decode output output group B3, but their detailed explanation will be omitted. However, as shown in FIG. 3, they are connected to a common constant current circuit H, and therefore only every second level shift circuit operates. However, in FIG. 3, the two level shift circuits of the level shift circuit RYSH3 shift the level to a value lower by two diode drop voltages than the decode output group B1 output from the level shift circuit SH. Decode output group B
An output terminal that outputs 3' is derived. Further, the level shift circuit group SH4 includes a predecoder PD
2f consisting of the (2'+1 to +2j+2) and 4th to (+2ft to 2+2j+2) bits from
Decode output group B4 of L bits is decoded output group 8
There are two level shift circuits that shift the level to 4';
As shown in FIG. 3, they have a configuration in which they are connected to a common constant current circuit H, and therefore only 2L level shift circuits operate. However, level shift circuit group S
The 2f1 level shift 1-circuits of H4 lead out output terminals as shown by solid lines in FIG. Furthermore, three level shift circuit groups 5H1SH and SH
The intermediate decoder FD decodes the bits of the three decode output groups ki from 3 to the decode outputs of the decode output group F. This intermediate decoder FD is the fourth decoder, although detailed explanation will be omitted.
As shown in the figure, NA using bipolar transistors
It has an ND type logic circuit configuration. In addition, the decode output by the decode output group F consisting of the first to second i+ bits from the intermediate decoder FD is level-shifted to the lower potential side and becomes 1÷j+l(2) consisting of the first to second i bits. Two level shift circuits HH1i+j+ which cause the decoded output group F' of bits i+j+ to level shift 1+j+.
It has a level shift circuit group HH consisting of 1b (b=2). Each level shift circuit H of this level shift circuit group HH)
1-H)-1, each has a configuration shown in FIGS. 5 to 7, although a detailed explanation will be omitted. Roughly speaking, the decode output from the three decode output group B4 of 2fL bits consisting of the jki (2+2 +2 +1) to (2+2j 10 + 2fL) bits from the level shift circuit group SH4, and the level shift circuit 1st to i+j+l< from group HH
i+j+l(2-bit decoding output group F consisting of 2 bits
The decoded output by +1 to 2J+j4 consisting of +jl bits from the first to second i+j+.
It has a main decoder MD that decodes into decode outputs of a decode output group G of bits. This main decoder MD is an N-type decoder using bipolar transistors, as shown in FIG. 8, although a detailed explanation will be omitted.
It has an AND type logic circuit configuration. Furthermore, 2i+j+l(+1
The decoded output group consisting of bits is the address signal A, as in the case of the conventional address decoder described above in Figure @11. 2i+j+l<+1 inverters 11 to I configured using MISffi field effect transistors as decoded outputs. (C=21+j++1). The above is the configuration of the embodiment of the address decoder according to the present invention. According to the address decoder according to the present invention, the address signal A. address signal A has a relatively small logic amplitude, as in the conventional address decoder described above in FIG. Since the four predecoders PD1 to PD4 that respectively decode the four address signal sections A-A4 constituting the circuit have a NOR type logic circuit configuration using bipolar transistors, ) 4 is above in Figure 11!
As in the case of predecoders PD1 and PD2 of the conventional address decoder, the address signal A. The four address signal sections A1 to A4 constituting the address signal section A1 to A4 are respectively decoded. Further, the main decoder MD is the main decoder MD, ~M in the conventional address decoder described above in FIG.
Like each of Da, it has a NAND type logic circuit configuration using bipolar transistors, so the main decoder MD has the same structure as the main decoders MD, ~MD, of the conventional address decoder described above in FIG. , its operation involves less power consumption. Further, the main decoder MD has a NAND type logic circuit configuration, and the main decoder MO has a decode output from the decode output group "from the intermediate decoder FD" and one pre-decoder from the four pre-decoders PD-PO2. A decode output consisting of a decode output from a decode output group B4 from the decoder PD4 is supplied, but a decode output from the decode output group F from the intermediate decoder FD and one pre-decoder PD4 among the n pre-decoders PD1 to PD4 are supplied. The decode outputs from the decode output group 84 are level-shifted by the level shift circuit group 1-1)-1 and one level shift circuit group SH4 in the four-hook level shift circuit group SH4. Since the decode outputs from the decode output groups F' and 84' are level-shifted and supplied, the main decoder MD becomes the main decoder MD of the conventional address decoder described above in FIG. , responds well. Furthermore, the main decoder MD has a NAND type logic circuit configuration, and the NAND type logic circuit configuration has a decode output from a decode output group F' from a level shift circuit group 1"1", 4 level shift circuit group SH-81
-14, the decode output from the decode output group B' from one level shift circuit group SH4
Since it is sufficient to have a configuration that only takes the D logic, decode outputs from the decode output group G having a relatively large logic amplitude are output. Furthermore, intermediate decoder FD also has N
Since it has an AND type logic circuit configuration, during its operation, the first
Like each of the main decoders MD1 to MD of the conventional address decoder described above in FIG. 1, and like the main decoder MD, only low power consumption is involved. Further, even if the intermediate decoder FD has a NAND type logic circuit configuration, the intermediate decoder FD has three predecoders P among the four predecoders PD to PD4.
The decode outputs from the three decode output groups 81 to B3 from D1 to PD3 are output to the four level shift circuit group SH1.
~ Decode output groups B1' to B that are level-shifted by three level shift circuit groups in S l-14, respectively.
Since the intermediate decoder FD is level-shifted and supplied to the decode output by 3', the intermediate decoder FD is similar to each of the main decoders MD1 to MD of the conventional address decoder described above in FIG. 11, and similarly to the main decoder MD. Respond well. From the above, according to the address decoder according to the present invention shown in FIG. 1, the address signal A has a relatively small logic amplitude, as in the case of the conventional address decoder described above in FIG. can be decoded into a decode output by the decode output group G having a large logic amplitude. However, in the case of the address decoder according to the present invention shown in FIG. 1, four predecoders PD are used as decoders.
Address signal A can be obtained by using only two other decoders, intermediate decoder FD and main decoder MD, in addition to PO4. can be decoded, so four predecoders PD1
~In the decoders excluding PD4, the power consumption is only 2/2 that of the conventional address decoder described above in FIG. 11. Furthermore, in the case of the address decoder according to the present invention shown in FIG. PD1~PD
4, one remaining predecoder PD4, one intermediate decoder FD, and one main decoder MD at the subsequent stage thereof. Therefore, address signals with the same number of bits can be decoded with the same number of bits. In order to decode the output, the number of level shift circuits (level shift circuit groups S H-S I-14 and HH are configured) is significantly smaller than in the case of the conventional address decoder described above in FIG. The level shift circuit therefore requires significantly less power consumption than in the conventional address decoder described above in FIG. 11. Incidentally, FIG. 9 shows the power consumption with respect to the number of bits of the decoded output group from the predecoder, using a specified current, in comparison with the case of the conventional address decoder described above in FIG. 11. Further, FIG. 10 shows address and signal A. The power consumption versus the number of bits of the decoded output group G is shown in comparison with the case of the conventional address decoder described above in FIG. 11, with similarly specified currents. From the above, in the case of the Natres decoder according to the present invention shown in FIG. 1, it is necessary to use a significantly smaller number of level shift circuits than in the case of the conventional address decoder described above in FIG. Significantly lower power consumption is involved than in the case of the conventional address decoder described above in FIG. 11. In addition, in the above, the case of n=4 was described, but
The same effects as described above can be obtained by setting n to a desired number of 3 or more, and various other modifications may be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a systematic connection diagram showing an embodiment of an address decoder according to the present invention. FIG. 2 is a connection diagram showing an embodiment of the predecoder. FIG. 3 is a connection diagram of an embodiment of the level shift circuit. FIG. 4 is a diagram showing FIGS. 4A and 4B. FIGS. 4A and 4B are connection diagrams showing an embodiment of the intermediate decoder. 5 to 7 are connection diagrams showing embodiments of the level shift circuit. FIG. 8 is a connection diagram showing an embodiment of the main decoder. FIGS. 9 and 10 are diagrams for explaining the effects of the address decoder according to the present invention. FIG. 11 is a systematic connection diagram showing FIGS. 11A and 8. FIGS. 11A and 11B are systematic connection diagrams showing a conventional address decoder. FIG. 12 is a connection diagram showing the address signal section output circuit. 13 to 15 are connection diagrams without showing the level shift circuit. FIG. 16 is a connection diagram showing the main decoder. PD-FD4... Pre-decoder SH, ~S
H4, HH...Level shift circuit group FD......Intermediate decoding MD, MD1 to MD.・・・・・・・・・Main decoder

Claims (1)

[Claims] n numbers constituting the address signal (n is an integer of 3 or more)
n predecoders each having a NOR type logic circuit configuration using bipolar transistors, each decoding the address signal from the address signal section of n first level shift circuit groups using bipolar transistors for level shifting, and (n-1) first level shift circuit groups among the n first level shift circuit groups; n-1
) an intermediate decoder having a NAND type logic circuit configuration using bipolar transistors to decode the decode outputs from the decode output groups; and a second level shift circuit to level shift the decode outputs from the decode output groups from the intermediate decoder. a decode output group from the second level shift circuit group, and a decode output group from the remaining first level shift circuit group among the n first level shift circuit groups. A bipolar transistor-based N
1. An address decoder comprising: a main decoder having an AND type logic circuit configuration.