JPH02172070A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To correct phase shift with low cost by providing an adjustment circuit for flow-out (INC) current and flow-in (DEC) current of a charge pump. CONSTITUTION:The circuit is provided with a phase comparator 1, a charge pump 2 having INC and DEC current adjustment circuit 13, a loop filter 3 and a VCO 4, a readout data signal 13 retarded for a prescribed time by a delay circuit 5 and a VCO clock 12 are inputted to a decoder 6 to demodulate a readout data signal 7. The INC and DEC current of the charge pump 2 is adjusted to synchronize the VCO clock while shifting the phase with respect to the readout data 7. Thus, while the delay of the readout data signal inputted to the decoder 6 is fixed, a window is deviated to attain adjustment while maximizing the window margin and the phase shift is corrected with low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization circuit in a magnetic disk drive.

[Conventional technology]

2. Description of the Related Art Conventionally, a phase synchronization circuit used for reproducing and demodulating a recorded signal in a magnetic disk drive or the like generally has a block configuration shown in FIG. 6.

The phase comparator 1 compares the phase of the read data signal 7 from the disk and the vC○ clock 12 output by the VCO 4, and if the phase of the read data signal 7 is ahead of the phase of the ■CO clock 12, the phase is compared by that time. INC borrowed name 8
On the other hand, if it is behind the VCO clock 12, the DEC signal 9 is output for that time. The charge pump 2 receives the INC signal 8 and the DEC signal 9 and performs a charging operation in accordance with the INC signal 8 and a discharging operation in accordance with the DEC signal 9. The loop filter 3 integrates and smooths the output 10 of the charge pump 2,
A VCO control voltage 11 is generated.

The VCO 4 has a frequency v corresponding to the vCO control voltage 11.
Output C○ clock 12. The phase synchronization circuit operates in this manner to match the phase of the vCO clock 12 with the phase of the read data signal 7.

The VC synchronized with the read data signal 7 in this way
The read data signal 13 delayed for a certain period of time by the O clock 12 and the delay line 5 is manually input to the decoder 6 to demodulate the read data signal.

Next, the operation of the delay line 19 will be explained using FIG. ■C
After the O clock 12 is input to the decoder 6, it becomes a window 14 by dividing the frequency by two.

When window 14 is open (in this case 11 HI+
The read data signal 13 input manually (at the time of level) is accepted and demodulated.

Generally, in a magnetic disk drive, a peak shift phenomenon of the read data signal 7 occurs due to magnetic interference on the disk. The range in which this peak shift phenomenon can be tolerated is called the wind margin, and is a major factor in determining the performance of a magnetic disk drive. In order to maximize this window margin, the delay amount of the delay line 19 should be set to half the period of the vC○ clock 12 so that the read data signal 13 input to the decoder 6 rises at the center of the window 14. good.

However, in reality, depending on the performance of the phase synchronization circuit, the VCO clock 12 and the read data signal 7 may not be completely synchronized and a phase shift may occur, resulting in a loss of wind margin.

Conventionally, in order to correct this phase shift, a tapped delay line 19 was used to adjust the amount of delay. This method requires an expensive delay line in order to finely adjust the amount of delay.

[Problem to be solved by the invention]

The above-mentioned conventional technology requires a high-precision delay line with taps, which poses a problem in terms of cost.

An object of the present invention is to provide a phase synchronization circuit that can correct the above-mentioned phase shift at low cost.

[Means to solve the problem]

In order to achieve the above object, an adjustment circuit is provided to change the current values of the INC current and DEC current of the charge pump.

[Effect]

By adjusting the INC current value and DEC current value of the charge pump, the CO clock can be synchronized with the read data signal with a phase shift. Thereby, the window margin can be adjusted to the maximum by shifting the window while keeping the delay amount of the read data signal input to the decoder fixed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a phase locked circuit according to the present invention. Current for adjusting phase comparator 1, INC, DEC current values: charge pump 2 with A adjustment circuit 13, loop filter 3, and VCO 4;
Synchronize C○ clock 12. vc synchronized with the read data signal 13 delayed for a certain period of time by the delay circuit 5
By inputting the o clock 12 to the decoder 6, the read data signal is demodulated.

The timing of the read data signal and the window will be explained using FIG. 2. The vCO clock 12 synchronized with the read data signal 7 by the phase synchronization circuit is frequency-divided by two by the decoder 6 to become a window 14. The read data 13 is converted into the read data 7 by the delay circuit 5.
This is delayed by a half period of the CO clock 12, and this allows the rise of the read data signal to be set at the center of the window 14, thereby maximizing the window margin.

However, in reality, the read data signal 13 may not be at the center of the window 14 depending on the performance of the phase locked loop.

Suppose now that the window 14 is out of phase as shown by the dotted line.

In this case, without changing the delay amount of the delay circuit 5, the current value of the INCNC current C current is adjusted by the current adjustment circuit 13 of the charge pump 2, and the ■C○ clock 12 is synchronized with a slightly advanced phase. so that the read data signal 13 comes to the center of the window 14.

The charge pump current adjustment circuit 13 of the present invention will be described with reference to FIGS. 3 and 4. FIG.

Figure 3 shows a circuit using a variable T current source for current regulation.
- INC variable current source 15, DEC variable current source 16, INC switch 17, DE C switch 1
It is composed of 8.

The INC signal 8 from the phase comparator 1 (FIG. 1) rises at the same time as the read data signal 7, and falls at a time corresponding to a half period of the VCO clock to be synchronized. DEC
The signal 9 rises simultaneously with the read data signal 7, and ■C
It falls simultaneously with the fall of the O clock 12. This INC signal 8. INC switch 17, DE in response to DEC signal 9
The C switch 18 turns ON and OFF, and the loop filter 3 is charged and discharged with current.

(Signal 10) Using Figure 4, output current value and
Explain the relationship with the phase.

The loop filter 3 receives the output current 10 of the charge pump 2.
, the co clock 12 becomes synchronous under the condition of I+NcXTt°IbxcXTz.

In the case of I IN (:> r DBc, the relationship T□<T2 holds true, so the CO clock 12 is synchronized with the read data signal after a delay of T2-T1.

On the other hand, ■, Nc work. . in the case of.

Since the relationship is T 1 > T 2 , the VCO clock 12 is synchronized with the read data signal by the time T, -T2.

From the above, it can be seen that the phase of the vCO clock 12 can be controlled by adjusting the INC current and DEC current.

FIG. 5 shows the INC current sources 15 and DE of the current adjustment circuit 13.
This is an example of the C current source 16.

In the figure, it can be constructed from PNP type transistors Ql and Q2 and a variable resistor R3, and by changing the variable resistor R3, the INC current or DEC current can be adjusted.

〔Effect of the invention〕

According to the present invention, the phase shift between the read data signal and the window can be corrected without using an expensive tapped delay line.
Since a variable resistor is used, it can be done at low cost.

Furthermore, since the phase can be controlled continuously instead of discrete adjustments such as selecting taps, more precise correction can be performed.

Furthermore, phase control can be performed by changing the resistance value, which is advantageous for IC implementation, automatic adjustment, etc.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram according to the present invention, FIG. 2 is a timing chart showing the operation of the present invention, FIG. 3 is a configuration diagram of an embodiment of a charge pump having a current adjustment circuit according to the present invention, and FIG.
The figure is a timing chart showing the operation of one embodiment of the present invention, and FIG. Block diagram of another embodiment, No. 6
FIG. 7 is a block diagram of a conventional phase-locked circuit, and FIG. 7 is a timing chart showing the operation of the conventional phase-locked circuit. 13...Current adjustment circuit 15...Variable INC current source 16...Variable DEC current source Tsukudomu Group/3 Atsushi Atsushi

Claims (1)

[Claims] 1. In a phase-locked circuit used when reproducing and demodulating data signals recorded in a magnetic recording device, a charge pump (hereinafter referred to as INC) constituting the phase-locked circuit is capable of draining (hereinafter referred to as INC) and drawing. (hereinafter referred to as DEC) A phase synchronized circuit comprising a current adjusting means for adjusting a current and adjusting a current value according to a phase shift between a data signal and a window. 2. The phase locked circuit according to claim 1, wherein a variable current source is used as the current adjusting means. 3. The phase locked circuit according to claim 2, wherein the variable current source is composed of a transistor and a variable resistor. 4. a phase comparison means, a charge pump means whose charge/discharge is controlled according to the output of the phase comparison means, a loop filter means for smoothing the output of the charge pump means, and an output of the loop filter means; It consists of a voltage-controlled oscillation means that controls the output frequency accordingly,
The phase comparison means is a phase synchronization circuit that compares the phases of the data signal and the output of the voltage controlled oscillation means, wherein the charge pump means includes two variable current source means for charging and discharging. circuit. 5. The phase-locked circuit according to claim 4, wherein the charge pump means comprises a series connection of two of the variable current source means and two switch means that are turned on and off according to the output of the phase comparison means. synchronous circuit.