JPH02151061A - Semiconductor device - Google Patents

Abstract

PURPOSE:To ensure a sufficient high resistance region and miniaturize a resistor by constructing the resistor nearly in U-shape in cross-section, and providing low resistance regions at the side parts of the U-shape and a high resistance region at the bottom part of the U-shape, and decreasing the spacing between both ends of the resistor. CONSTITUTION:A semiconductor substrate 50, an insulator 51, and a resistor 52 are comprised. The resistor 52 is constructed nearly in U-shape in cross-section, and provided with low resistance regions 52a at the side parts of the U-shape and a high resistance region 52b at the bottom part of the U-shape. In particular, the high resistance region 52b is formed at a position deeper than both ends of the low resistance regions of 52a, and both ends of the low resistance regions 52a are on the same plane nearly parallel to the plane of the semiconductor substrate 50 and in contact with electrodes 53 on the semiconductor substrate 50. Thus, the high resistance region 52b can sufficiently be ensured, and moreover, the spacing between both ends of the resistor 52 can be made small so that miniaturized construction can be achieved.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having a resistor covered with an insulator on a semiconductor substrate, it is possible to secure a sufficient high resistance region, and furthermore, the distance between both ends of the resistor can be made small, resulting in a small size. The resistor has a roughly U-shaped cross section, with a low-resistance region on the side of the U-shape and a high-resistance region on the bottom of the U-shape. do.

(Industrial Application Field) The present invention relates to a semiconductor device having a resistor covered with an insulator on a semiconductor substrate.

Conventionally, when forming a resistor in a semiconductor substrate, PN junction isolation is used, so that a junction capacitance is equivalently formed at the PN junction, which hinders high-speed operation. Therefore, now that high speed is an important issue, a resistor is formed in a plane on an insulator on a substrate, and its surroundings are covered with an insulator so that no PN junction is formed. What has been done is becoming mainstream.

In a semiconductor device having such a resistor, a sufficient high-resistance region can be secured, and good contact can be made between the resistor and the electrode.Moreover, in today's world where miniaturization of devices is desired, It is necessary to reduce the distance between both ends of the resistor to make it compact.

(Conventional technology) FIG. 4 shows a structural sectional view of an example of a conventional device.

In the figure, a silicon oxide film 2 is formed on a silicon substrate 1, and a polycrystalline silicon layer 3 is deposited on the surface thereof. High concentration N+ layers (low resistance) 3a are formed at both ends of the polycrystalline silicon W43 by doping, and a low concentration layer (high resistance) 3b is formed between them. The resistance value is mainly determined by the high resistance low concentration layer 3b.

The periphery of the polycrystalline silicon layer 3 is covered with a silicon oxide film 4, and the high concentration layer 3a is in contact with an electrode 5 made of aluminum or the like through a contact window 4a. The high concentration layer 3a and the low concentration layer 3b are formed by doping the polycrystalline silicon layer 3 through the contact window 4a and then performing a heat treatment to diffuse dopants. High concentration layer 3
Since a has a low resistance, good contact with the electrode 5 can be made. This device is used, for example, with the electrode 5 connected to the emitter region, collector region, etc. of an adjacent transistor (not shown).

(Problems to be Solved by the Invention) The conventional device shown in FIG.
When forming the concentration layer 3a, after doping the polycrystalline silicon 113, the introduced dopant is activated by heat treatment. This portion requires a sufficient carrier concentration in order to make good contact with the electrode 5.

However, in general, dopants diffuse quickly in polycrystalline silicon, and when activated by the heat treatment described above, a high concentration l! 3a
dopant diffuses laterally. For this,
Low concentration 1i, which should originally be low concentration (high resistance)
3b is actually much shorter than the length shown in the figure, and there is virtually no high resistance region, which causes a sharp problem in that a sufficiently high resistance value cannot be obtained.

Therefore, in order to eliminate this problem, the length of the picture electrode 5fi, that is, the polycrystalline silicon layer 3, must be set sufficiently long, and the high concentration layer 3 can be activated by heat treatment.
The configuration is such that even if the dopant a diffuses in the lateral direction, it does not affect the low concentration 113b. However, in this case, the length between the picture electrodes 5 becomes long, and there is a problem in that it cannot be constructed in a compact size, or in other words, it hinders integration.

In addition, in the activation by the heat treatment, there is generally a relationship that the diffusion distance is long when the concentration is high, and the diffusion distance is short when the concentration is low, so in order to secure the low concentration layer 3b described above, In the initial stage, the high concentration layer 3a must also be made low in concentration.

However, although the low concentration layer 3b is secured in this way, the main angle of 711 degrees of the high concentration layer 3a cannot be sufficiently maintained, and as a result, this portion does not have a sufficiently low resistance, and the electrode 5
There was a problem with poor contact with the

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can sufficiently secure a high resistance region and can be constructed in a compact size by reducing the distance between both ends of a resistor.

(Means for Solving the Problems) FIG. 1 shows a principle diagram (cross-sectional view) of the present invention. Same figure (A)
Inside, 50 is a semiconductor substrate, 51 is an insulator, and 52 is a resistor. The resistor 52 has a generally U-shaped cross section, and includes a low resistance region 52a1 on the side of the U shape and a high resistance region 52b on the bottom of the U shape.

In this case, in particular, as shown in FIG. 1(B), the high resistance region 52b is formed at a deeper position than both ends of the low resistance region 52a. Further, both ends of the low resistance region 52a are on the same plane that is approximately parallel to the plane of the semiconductor substrate 50, and are in contact with the electrode 53 on the semiconductor substrate 50.

Furthermore, as shown in FIG. 1(C), a high resistance region (52b)
are formed at shallower positions than both ends of the low resistance region 52a. Further, both ends of the high resistance region 52b are connected to the semiconductor substrate 50.
Diffusion formed in W! Connected to i54.

[Effect]

In the present invention, since the resistor 50 is configured in a U-shape,
If the depth of the U-shaped side portions is long, the low resistance region 52 can be formed by heat treatment without requiring a large interval between the U-shaped ends.
When forming a, the impurity diffusion at 811 degrees can be prevented from reaching the high resistance region 52b, and the high resistance region 52b can be sufficiently secured.

In particular, when the electrode 53 is connected to the end of the low resistance region 52a, good contact with the electric bridge 53 can be achieved.
Moreover, a sufficient high resistance region can be secured, the interval between picture electrodes can be reduced, and the device can be miniaturized.

Furthermore, in the case of a transistor connected to an adjacent transistor through a buried region, a sufficient amount of the high resistance region 52b can be secured and the interval between the ends of the low resistance region 1a52a can be made small, and furthermore, it is possible to provide an external electrode. Since it can be connected to an adjacent transistor even if the transistor is not connected, the device can be further miniaturized.

〔Example〕

FIG. 2 shows I33 & process drawings (sectional view and plan view) of an embodiment of the apparatus of the present invention. As shown in FIG. 2(A), CVD is applied to the surface of the silicon substrate 10 (P<100>10.1).
A silicon oxide layer 11 with a thickness of 0.1 .mu.m is formed by a method, and a silicon nitride layer 12 with a thickness of 0.3 .mu.m is further formed on this surface by a CVD method. Next, as shown in FIG. 2(B), a patterned resist film 13 is placed and anisotropic etching is performed using this as a mask to remove the silicon nitride layer 12.
．． 1! Illized silicon layer 11. A U 14 is formed over the silicon substrate 10. Next, as shown in FIG. 2C, when isotropic etching is performed, the silicon nitride layer 12 is hardly etched, and the silicon oxide layer 11 and the silicon substrate 10 are etched to a width wider than the U-groove 14. A wide U-groove 15 is formed, and an eaves portion 12a is formed of silicon nitride Wi12.

The hole 12b formed by the eave part 12a is shown in FIG. 2(C).
In the plan view shown in , it is formed, for example, in a rectangular shape.

Next, as shown in FIG. 2(D), oxidation is performed to form the U groove 1.
A silicon oxide layer 11a having a thickness of 0.3 μm is formed within the silicon oxide layer 5. After this, the energy is 50 keV.

Silicon ion implantation is performed under the following conditions: dose-ffiIX101'cII. In this case, ion implantation is performed in the vertical and oblique directions to form the damaged layer 16 only on the pair of side walls and the bottom surface of the U-groove 15.

Next, using trichlorosilane as the growth gas, as shown in Fig. 2 (E
), polycrystalline silicon 1117 is grown to a thickness of 02 μm. In this case, a U-shaped polycrystalline silicon layer 17 is formed only on the damaged layer 16 formed on the sidewalls and bottom surface by implanting silicon. Next, oxidation is performed to form a silicon oxide layer 18 with a thickness of 0.2μ on the surface of the polycrystalline silicon layer 17, as shown in FIG. 2(F).
A polycrystalline silicon layer 19 is grown within the trench. Next, as shown in FIG. 2(G), polishing is performed to flatten the surface.

Next, as shown in FIG. 2H, a silicon oxide layer 20 with a thickness of 0.5 μm is formed on the surface by CVD, and a contact window 20 is formed in the silicon oxide layer 20 so that the polycrystalline silicon 117 is exposed. Form .22.

Next, the energy is 50 keV, the dose [t2X10”oM
'Polycrystalline silicon r! For example, ion implantation of arsenic (other substances may be used) is performed on J17, and then,
A heat treatment is performed at 1100° C. for 10 seconds in a dry oxygen atmosphere to activate the dopant introduced into the polycrystalline silicon layer 17. Due to the dopant diffusion caused by this activation, U
A high concentration layer 17a is formed on the sides of the polycrystalline silicon layer 17 formed in the shape of a letter, while a low concentration layer 17b is formed on the bottom of the polycrystalline silicon layer 17.
is formed. Next, during activation, the silicon oxide layer 20
After etching the silicon oxide film formed on the surface to a thickness of about 50 r+m, an aluminum layer is deposited on the surface, and the portion of the aluminum layer facing the polycrystalline silicon layer 17 is left by etching to form the electrodes 23 and 24. .

Thereby, the low concentration (high resistance) layer 1117b is connected to the electrodes 23.24 via the high concentration (low resistance) layer 17a.

As described above, in the present invention, the polycrystalline silicon layer 17 is formed in a U-shape in the silicon substrate 10, and the high concentration (low resistance) layer 17a and the low concentration (high resistance) layer 1117b are formed therein. If the depth of the side portions of the U-shape is made long, it is possible to form the high concentration layer 17a and the low concentration layer 17b by activation by heat treatment, without having to make a large interval between the electrodes 23 and 24 as in the conventional example. It is possible to prevent diffusion of the dopant in the high concentration tFJ 17a into the low concentration layer 17b,
Enough high resistance area can be secured. This is the electrode 23
．． 24 is used by being connected to the emitter region, collector region, etc. of an adjacent transistor (not shown).

FIG. 3 shows a manufacturing process diagram (cross-sectional view) of another embodiment of the present invention. As shown in FIG. 3(A), a silicon substrate 30
(P <100> 1Ω・cJ) N+ diffusion layer 31.32 is selectively formed on the surface, and a 3 μl thick layer is formed on the surface.
A silicon oxide layer 33 is deposited, and then an N+ diffusion layer 3
Holes 34 and 35 are formed by etching the silicon oxide layer 33 so that 1.32 is exposed. At this time, VJ)? The emitter region of the transistor 38. A base region 39° and a collector region 40 are also created. In this case, the N+ diffusion layers 31 and 32 become the buried collector region of the transistor. Next, as shown in FIG. 3(B), the inside of the hole 34°35 and the silicon oxide W! 1 μl thick polycrystalline silicon 1 on the surface of J33! ! 36 is grown and then formed as shown in FIG. 3(C).
As shown in FIG. 3, both ends of the polycrystalline silicon layer 36 formed on the surface are etched away to form an inverted U-shaped polycrystalline silicon layer 1136.

Next, heat treatment is performed to diffuse impurities in the N+ diffusion layers 31 and 32 into the polycrystalline silicon layer 36. Note that this heat treatment can also serve as emitter formation heat treatment. As a result, a high concentration layer 36a is formed on the sides of the polycrystalline silicon layer 36 formed in an inverted U shape, while a low concentration layer 36b is formed on the bottom thereof. Next, as shown in FIG. 3(D), a silicon oxide layer 37 with a thickness of 1 μm is formed on the surface. As a result, the low concentration (high resistance) layer 36b, the high concentration (low resistance) layer 36a, the N+ diffusion layer (buried collector region) 31
connected to the transistor via.

In this case as well, similarly to the above-mentioned embodiment, a polycrystalline silicon layer 36 is formed in an inverted U shape, and a high concentration (low resistance) layer 3 is formed thereon.
6a and a low concentration (high resistance) layer 36b, if the depth of the sides of the inverted U shape is made long, it is possible to increase the distance between both ends of the resistor in a plan view as in the conventional example. No but N
Diffusion from the first diffusion layers 31 and 32 can be prevented from reaching the low concentration Fi 36b, and a sufficient high resistance region can be secured. Furthermore, since this embodiment has a configuration that allows connection to adjacent transistors without providing external electrodes, the area on the plan view can be reduced compared to a configuration in which electrodes are provided and connections are made to transistors via the outside. can.

Although the present invention is effective in forming a high resistance element, it is also effective in forming a resistor having a relatively low resistance and a homogeneous gear rear resistor.

(Effects of the Invention) As explained above, according to the present invention, even if the distance between both ends of the low resistance region is not large, the diffusion of high concentration impurities is increased when forming the low resistance region and the high resistance region by heat treatment. It is possible to prevent this from reaching the resistance region, to ensure a sufficient high resistance region, and therefore to miniaturize the neck attachment. In particular, in the case where the electrode is connected to the edge of the low-resistance area, good contact with the electrode can be made, and a sufficient high-resistance area can be secured, allowing the distance between the picture electrodes to be reduced. For devices connected to adjacent transistors via regions, the device can be further miniaturized.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention (cross-sectional view), Fig. 2 is a manufacturing process diagram (cross-sectional view, plan view) of one embodiment of the present invention, and Fig. 3 is a manufacturing process diagram of another embodiment of the present invention. FIG. 4 is a sectional view of a conventional structure. 50 is a semiconductor substrate, 51 is an insulator, 52 is a resistor, 52a is a low resistance region, 52b is a high resistance region, and 54 is a small diffusion layer.

Claims (1)

[Claims] [1] In a semiconductor device having a resistor (52) covered with an insulator (51) on a semiconductor substrate (50), the resistor (52) has a substantially U-shaped cross section. A semiconductor device comprising: a low-resistance region (52a) on a side of the U-shape, and a high-resistance region (52b) on a bottom of the U-shape. [2] In the semiconductor device according to claim (1), the high resistance region (52b) is formed at a deeper position than both ends of the low resistance region (52a), and both ends of the low resistance region (52a) is a semiconductor substrate (50)
A semiconductor device, characterized in that it is located on the same plane approximately parallel to a plane and is in contact with an electrode (53) on the semiconductor substrate (50). [3] In the semiconductor device according to claim (1), the high-resistance region (52b) is formed at a shallower position than both ends of the low-resistance region (52a), and both ends of the high-resistance region (52b) is a semiconductor substrate (50)
A semiconductor device characterized in that the semiconductor device is connected to an impurity layer (54) formed in the semiconductor device.