JPH02144627A - Method and device for inference using hardware - Google Patents

Method and device for inference using hardware

Info

Publication number
JPH02144627A
JPH02144627A JP63298578A JP29857888A JPH02144627A JP H02144627 A JPH02144627 A JP H02144627A JP 63298578 A JP63298578 A JP 63298578A JP 29857888 A JP29857888 A JP 29857888A JP H02144627 A JPH02144627 A JP H02144627A
Authority
JP
Japan
Prior art keywords
inference
memory
address
addresses
conclusion part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63298578A
Other languages
Japanese (ja)
Inventor
Atsushi Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP63298578A priority Critical patent/JPH02144627A/en
Publication of JPH02144627A publication Critical patent/JPH02144627A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To rapidly execute inference by using data read out from an inference memory as the succeeding address to advance inference, and when a control word for the read data indicates user interface access storing an established fact in a check bit of the inference memory.
CONSTITUTION: When the conclusion part of B is obtained at the time of specifying the address of A, the address of B is specified to obtain the conclusion part of C, so that inference from A to B and B to C can be advanced. In relation between addresses and the number of bits of data, the number of bits for addresses is not increased as compared to an existing inference system and is set up almost to the same value, and when only one condition part and one conclusion part exist, one rule is stored in one address. Since an inference program does not exist by advancing inference by hardware in a CPU, the whole memory capacity of the memory can be used for storing rules, so that rules corresponding to memory addresses can be stored. Thus, rapid inference can be executed.
COPYRIGHT: (C)1990,JPO&Japio
JP63298578A 1988-11-25 1988-11-25 Method and device for inference using hardware Pending JPH02144627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63298578A JPH02144627A (en) 1988-11-25 1988-11-25 Method and device for inference using hardware

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63298578A JPH02144627A (en) 1988-11-25 1988-11-25 Method and device for inference using hardware

Publications (1)

Publication Number Publication Date
JPH02144627A true JPH02144627A (en) 1990-06-04

Family

ID=17861556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63298578A Pending JPH02144627A (en) 1988-11-25 1988-11-25 Method and device for inference using hardware

Country Status (1)

Country Link
JP (1) JPH02144627A (en)

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