JPH0213858A - Apparatus for storing data in memory - Google Patents

Abstract

PURPOSE:To store a measuring waveform signal for a long time while reducing a memory number in a part where a waveform change is small by storing the digital data of an A/D converter and the coincidence number of samples in a memory only when said digital data is changed. CONSTITUTION:An analogue signal is converted to a digital signal by an A/D converter and, at each time when this digital data is changed, the output digital data thereof is latched by a latch circuit 2. The output digital data of the A/D converter 1 is compared with the latch digital data of the latch circuit 2 by a comparing circuit 3 to count the coincidence number of samples by a counter 4. At each time when the latch digital data of the latch circuit 2 is changed, said latch digital data and the coincidence number of samples are stored in a memory 5 storing data. By this method, as compared with a case storing data in the memory 5 at every sampling, memory quantity is reduced by the quantity corresponding to the number of digital data coinciding continuously and digital data many by the reduced quantity can be stored in the memory 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data memory storage device suitable for use, for example, in a waveform storage device.

[Summary of the invention]

The present invention provides a data memory storage device suitable for use in a waveform storage device, for example, which includes an A-D converter that converts an analog signal into a digital signal, and an A-D converter that converts an analog signal into a digital signal every time the digital data of the A-D converter changes. a latch circuit that latches the output digital data of this A-Di converter, and a latch circuit that latches the output digital data of this A-Di converter;
It has a comparison circuit that compares the output digital data of the converter and the latched digital data of this latch circuit, a counter that counts the number of matching samples of this comparison circuit, and a memory that stores the data. By storing the digital data and the number of matching samples each time the latch digital data of the launch circuit changes, it is possible to store more data in the memory.

[Conventional technology]

In data memory storage devices that are generally used in waveform storage devices, analog waveform data is converted into digital data by an A converter that converts analog signals into digital signals, and the data is stored sample by sample in the memory. It was designed to be stored sequentially.

[Problem to be solved by the invention]

Conventional data memory storage devices require a memory capacity corresponding to the number of samples, so it is necessary to increase the number of samples in a relatively small memory to store digital data with relatively high reproducibility. When this is done, only short-time waveforms can be stored, and when the number of samplings is reduced in order to store (record) the waveforms for a long time, the reproducibility of the waveforms becomes poor.

In view of these points, it is an object of the present invention to provide relatively good reproducibility of waveforms, etc., and to enable storage for a relatively long period of time.

[Means to solve the problem]

The data memory storage device of the present invention includes, for example, an A-D converter (1) that converts an analog signal into a digital signal, as shown in FIG. A latch circuit (2) that latches the output digital data of the A-D converter +1) and this A-
A comparison circuit (3) that compares the output digital data of the D converter (1) with the launch digital data of this latch circuit (2), and a counter (4) that counts the number of matching samples of this comparison circuit (3). ) and a memory for storing data (5
), and this memory (5) has this latch circuit (2)
Each time the launch digital data changes, this digital data and the number of matching samples are stored.

[Effect]

According to the present invention, only when the digital data of the A-D converter (1) changes, this digital data and the number of matching samplings are stored in the memory (5), so that a memo month can be stored for each sampling. Compared to the case of storing in 5), the amount to be stored is reduced by the amount of consecutively matching digital data, and more digital data can be stored in the memo 5) by this reduced amount.

〔Example〕

An embodiment of the data memory storage device of the present invention will be described below with reference to FIG.

In FIG. 1, (6) indicates a waveform signal input terminal to which a measurement waveform signal (7) to be recorded, such as an electroencephalogram, as shown in FIG. The supplied measurement waveform signal (7) is supplied to an A-D converter (1) that converts an analog signal into a digital signal. This A
- For example, a successive approximation type AD converter is used as the D converter (1). This successive approximation type A-D converter has a faster conversion speed than the pulse counting type A-D converter, for example, 1
In this example, this A-Di converter (1) has the advantage of having a 2-bit resolution and a conversion speed of 1 μ3 to 50 μs.
This A-D converter (1) generates a start conversion signal (8) synchronized with the sampling clock pulse as shown in FIG. 2A from the timing controller (8).
Analog-to-digital conversion is started by a), and at this time, the A-L) converter (1) sends 1iu as a status to the timing controller (8) as shown in FIG. 2B.
sy signal (1a) is sent. The 12-bit output digital data (1) of this A-L) conversion 55(1)
b) is supplied to the comparison circuit (3) and the latch circuit (2), respectively.

This latch circuit (2) is an inverter circuit (9) which will be described later.
When the output signal rises, the output digital data (1b) of the A-D converter (11) is launched.The launch digital data (2a) of this latch circuit (2) is supplied to the comparator circuit (3), and This 12-bit launch digital data (2a) is supplied to a 16-bit buffer circuit (lO).In this comparison circuit (3), a start conversion signal as shown in FIG. 2E from a timing controller (8) is supplied. Every time a comparison enable signal (8b) having a predetermined phase difference from (8a) is supplied, output digital data (1b) and latch circuit (2) as shown in FIG. 2C of the A-D converter (1) are supplied. ) with the rough digital data (2a) shown in Figure 2j,
Only when these do not match, a mismatch signal (3a) as shown in FIG. 2F is output. Also, the start conversion signal (8) from the timing controller (8)
A) is supplied to, for example, a 4-bit counter (4), and this counter (4) counts the number of samples of the A/D converter (1). The 4-bit count signal of this counter (4) is supplied to a 4-bit latch circuit (11). In this latch circuit (11), a comparison circuit (
The mismatch signal (3a) obtained at the output side of step 3) is latched by the rise of the launch command signal (13a) as shown in FIG. 2G via the OR circuit (12) and the play circuit (13). The 4-bit latch counter data (lla) obtained on the output side of the latch circuit (11) is supplied to the buffer circuit (10). This buffer circuit (10
), 12-pin latch digital data (2a) from the latch circuit (2) and 4-bit counter data (Ila) from the latch circuit (11) are supplied. In this case, the counter (4) counts the start conversion signal (8a) and is cleared by the mismatch signal (3a), so this counter (4) counts the start conversion signal (8a).
This means that the number of coincident samplings of the output digital data (1b) of 1) is counted. Further, the mismatch signal (3a) as shown in FIG.
) and an inverter circuit (9) to the timing controller (8), and also to the latch control terminal of the latch circuit (2) and the clear terminal of the counter (4), respectively. In this case, the output side of the inverter circuit (9) has 88
As shown in Figure 2, the mismatch signal (3a) is delayed and an inverted command signal (9a) is obtained, and the rise of this command signal (9a) causes the latch circuit (2) to
The output digital data (1b) of the D variable pAm (1) is latched and the counter (4) is cleared. Further, the launch circuit (11) launches the counter data before the counter (4) to be latched is cleared by the latch command signal (13a) obtained at the output side of the play circuit (13). Further, a command signal is supplied to the timing controller (8) from the output side of the inverter circuit (9), so that the timing controller (8) is supplied with a command signal from the output side of the inverter circuit (9).
) supplies a tri-state enable signal to the buffer circuit (10) at this time;
) 12-bit digital data (2a
) and 4-bit counter data (lla) are stored in RAM (5) constituting the memory with 16 bits as shown in FIG. 2K.
It is written as bint data (10a) at the address specified by the timing controller (8). Also, in this example, the counter (4)
When overflow occurs, a carry signal is output, and this carry signal is supplied to the OR circuit (12). At this time, the operation is the same as when the mismatch signal (3a) is obtained at the output side of the comparator circuit (3). As if to do this, this power (4)
) so that there will be no inconvenience even when it overflows.

Next, the operation of the memory storage device for data in this example will be explained with reference to FIG.
), the start conversion signal (1a) is A-D*
When supplied to converter (1), this A-D converter (1)
converts the input analog signal into a digital signal, and at this time supplies a BUSY signal as shown in FIG. 2B from the A-D converter (1) to the timing controller (8),
At this time, a start conversion signal (8a) is also supplied to the counter (4).

Now this first one. Second. Third. The fourth start conversion signal is supplied, and the output digital data of the A-D converter (1) is Do as shown in Figure 2C, and the second and third are the same Di. .

L) It is assumed that the first output digital data Do is latched by the latch circuit (2) and the counter (4) is cleared.

At this time, the start conversion signal (8a) is A-D.
When it is supplied to the converter (1) and also to the counter (4), this counter (4) becomes "1", and at this time, the output digital data D1 is sent to the comparator circuit (3) and the latch circuit (2). is supplied, and since this output digital data D1 is different from the latch digital data Do of the latch circuit (2), a comparison enable signal (8b) as shown in FIG. 2E is supplied to the comparator circuit (3) at this time. When this occurs, a mismatch signal (3a) is obtained on the output side as shown in FIG. 2F, and this mismatch signal (3a) is delayed on the output side of the play circuit (13) as shown in FIG. 2G. A launch command signal (13a) as shown in FIG. The command signal (13a) is sent to the play circuit (
A command signal (9a) as shown in FIG. At this time, the latch digital data Do of the latch circuit (2) and the latch counter data "1" of the latch circuit (11), that is, the number of matching samples, are supplied as shown in FIG. 2H. Write to the specified location of RAM (5), and at the timing of the rise of this command signal (9a), latch the output digital data D1 of the A-D converter +11 in the latch circuit (2) and clear the counter (4). The 0th order start conversion signal (8a) is supplied to the A-D converter (1), where it is A-D converted and also supplied to the counter (4), and when the count data is set to "1", the output digital data D1 is Since it is the same as the latch digital data D1 of the latch circuit (2), at this time, the comparison circuit (3) is supplied with a comparison enable signal (
Even if 8b) is supplied, no mismatch signal is obtained and nothing is stored in the RAM at this time. In history, when the next start conversion signal (8a) is supplied to the A-D converter (1) and also supplied to the counter (4), this counter (4) becomes "2" as shown in the second figure. , At this time, the comparison circuit (3) and latch circuit (2) are replaced with this A-Di! The output digital data D2 of (1) is supplied, and at this time, this output digital data D2 and the latch circuit (
2), so when the comparison circuit (3) is supplied with the comparison enable signal (8b) as shown in FIG. 2H, the second
A mismatch signal (3a) as shown in FIG. H is obtained, and a latch command signal (13a) as shown in FIG. This latch command signal (13a) causes the latch circuit (11) to latch the count data "2" of the counter (4) as shown in FIG. The command signal as shown in FIG.
9a) is supplied to the timing controller (8), and a tri-state enable signal is supplied to the buffer circuit (10) at the falling timing of this command signal (9a), and at this time, the latch circuit is activated as shown in FIG. 2H. The latch digital data D1 of (2) and the latch counter data "2" immediate match sample number of the latch circuit (11) are stored in RAM.
(5), and then write this command signal (9a
) The output digital data D2 of the A-D converter (1) is latched in the latch circuit (2) at the rising edge of the signal D2, and the counter (4) is also cleared. It is. More specifically, RAM
(For the data stored in 51, the measurement waveform signal (7) as shown in FIG. 3 is input to the combined waveform signal input terminal (6).
is supplied, and the sampling point is 261 with O to 25.
When the data is fixed, the following information is stored in RAM (5) in this example.

That is, since the quantization amount of the first θ~9 sampling points of this measurement waveform signal (7) is "6", the digital data is "6" at the sampling point "lO", that is, r AOO6J RAM
15), and the next two sampling points have a quantization amount of "7", so at the 12th sampling point, the digital data is stored in RAM (5), for example, at address 2 with a sampling number of "2". "7" i.e. r 200
7J and sequentially store r at the 3rd address at 13 sampling points.
1006J, r2 at the 4th address at 15 sampling points
005J, r10 at the 5th address with 16 sampling points
09J, "100" is placed at the 6th address at the 17th sampling point.
mouth".

rloooEJ at the 7th address at 18 sampling points, 1
rlooDJ at address 8 with 9 sampling points, 20
rlo09J at the 9th address at the sampling point, r1004J at the 10th address at the 21st sampling point, 22
At the sampling point, "1002" is stored at the 11th address, at the 23rd sampling point, r1005J is stored at the $12 address, and at the 25th sampling point, r2007J is stored at the 13th address.

Next, this RAM (to read 51, use RAM
The signals are read in the storage order of (5) and supplied to a D-A converter circuit that converts the digital signals into analog signals. In this case, the original measurement waveform signal can be reproduced by supplying this digital data to the DA converter circuit a number of times corresponding to the number of samplings.

Therefore, in this example, when the change in the measured waveform signal (7) is small, the number of memories will be small. There is an advantage that the number is reduced and the measurement waveform signal can be stored for a long time. In the example shown in FIG. 3, the number of sampling points is 26, but the number of sampling points to be stored is 13, which provides good benefits.

In addition, in this example, since digital data and the number of consecutive samplings of the same digital data are stored in RAM (5), the amplitude distribution of the measured waveform can be easily determined by reading this RAM (5). A histogram is obtained.

It goes without saying that the invention of the face tree is not limited to the above-described embodiments, and can take various other configurations without departing from the gist of the invention.

〔Effect of the invention〕

According to the present invention, for example, when the change in the measured waveform signal is small, the number of memories is small, so even if the number of samplings is relatively large to improve waveform reproducibility, the number of memories is small in parts where the waveform change is small. Therefore, there is an advantage that the measured waveform signal can be stored for a long time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a data memory storage device of the present invention, and FIGS. 2 and 3 are diagrams for explaining the present invention, respectively. (1) is an A-D converter, (2) and (11) are latch circuits, (3) is a comparison circuit, (4) is a counter, and (5) is R
AM, (6) is a measurement waveform signal input terminal, (8) is a timing controller, and (10) is a buffer circuit.

Claims (1)

[Claims] an A-D converter that converts an analog signal into a digital signal; a latch circuit that latches the output digital data of the A-D converter every time the digital data of the A-D converter changes; It has a comparator circuit that compares the output digital data of the converter and the latched digital data of the latch circuit, a counter that counts the number of matching samples of the comparator circuit, and a memory that stores data. A data memory storage device characterized in that each time the latch digital data of a circuit changes, this digital data and the number of matching samples are stored.