JPH02136945A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPH02136945A
JPH02136945A JP29099688A JP29099688A JPH02136945A JP H02136945 A JPH02136945 A JP H02136945A JP 29099688 A JP29099688 A JP 29099688A JP 29099688 A JP29099688 A JP 29099688A JP H02136945 A JPH02136945 A JP H02136945A
Authority
JP
Japan
Prior art keywords
memory
bank busy
waiting time
bank
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29099688A
Inventor
Yuzo Omori
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP29099688A priority Critical patent/JPH02136945A/en
Publication of JPH02136945A publication Critical patent/JPH02136945A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To combine various timings of the waiting time for memory accesses in a high load state and to acceleratively evaluate a system by producing artificially a bank busy state for a prescribed period of time in addition to an original bank busy state of a main memory.
CONSTITUTION: The contents of a pseudo bank busy memory 9 are set at the value designated by an initialization circuit 13. In other words, the pseudo bank busy signals 300 are produced in each prescribed machine cycle and in a repeating pattern for each bank based on the contents of the memory 9. Thus various timing combinations of the waiting time for memory accesses are obtained by setting previously the memory 9 so that a bank busy state necessary for the system evaluation is attained. As a result, the various timing combinations of the waiting time for memory accesses are obtained in a high load state and the accelerative system evaluation is attained with high efficiency.
COPYRIGHT: (C)1990,JPO&Japio
JP29099688A 1988-11-17 1988-11-17 Memory controller Pending JPH02136945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29099688A JPH02136945A (en) 1988-11-17 1988-11-17 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29099688A JPH02136945A (en) 1988-11-17 1988-11-17 Memory controller

Publications (1)

Publication Number Publication Date
JPH02136945A true JPH02136945A (en) 1990-05-25

Family

ID=17763111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29099688A Pending JPH02136945A (en) 1988-11-17 1988-11-17 Memory controller

Country Status (1)

Country Link
JP (1) JPH02136945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012181916A (en) * 2005-09-30 2012-09-20 Mosaid Technologies Inc Multiple independent serial link memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012181916A (en) * 2005-09-30 2012-09-20 Mosaid Technologies Inc Multiple independent serial link memory

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