JPH02135754A - Manufacture of semiconductor substrate - Google Patents
Manufacture of semiconductor substrateInfo
- Publication number
- JPH02135754A JPH02135754A JP28873588A JP28873588A JPH02135754A JP H02135754 A JPH02135754 A JP H02135754A JP 28873588 A JP28873588 A JP 28873588A JP 28873588 A JP28873588 A JP 28873588A JP H02135754 A JPH02135754 A JP H02135754A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- molten
- silicon dioxide
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 63
- 239000010703 silicon Substances 0.000 claims abstract description 63
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000010408 film Substances 0.000 claims abstract description 58
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 31
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000203 mixture Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 12
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 101100473036 Mus musculus Hnrnpa1 gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分舒)
この発明は、半導体集積回路に用いられろ半導体基体の
製造方法に係り、詳しくは、半導体基板の溝内を含む表
面に二酸化シリコン膜を形成し、その上に、溶融シリコ
ンの被着固化により多結晶シリコン層を形成する方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application) The present invention relates to a method for manufacturing a semiconductor substrate used in a semiconductor integrated circuit. The present invention relates to a method for forming a polycrystalline silicon layer thereon by depositing and solidifying molten silicon.
(従来の技術)
半導体基板の溝内を含む表面に二酸化シリコン膜を形成
し、その上に、溶融シリコンの被着固化により多結晶シ
リコン層を形成する方法は、−例として誘電体分離基板
の製ft法に応用されろ。そこで、従来の上記方法とし
て、従来のg電体分離基板の製造法について第2図を参
照して説明する。(Prior art) A method of forming a silicon dioxide film on the surface of a semiconductor substrate including the inside of a groove, and forming a polycrystalline silicon layer thereon by adhering and solidifying molten silicon is as follows. It should be applied to the manufacturing ft method. Therefore, as the above-mentioned conventional method, a conventional method for manufacturing a g-electrical isolation substrate will be described with reference to FIG.
この誘電体分離基板の製造法は、特開昭60−1827
38号公報に開示される。The manufacturing method of this dielectric isolation substrate is disclosed in Japanese Patent Application Laid-Open No. 60-1827.
It is disclosed in Publication No. 38.
まず、第2図(alに示すように、単結晶シリコン基板
1を異方性エツチングし、V字溝2を形成する。First, as shown in FIG. 2(al), a single crystal silicon substrate 1 is anisotropically etched to form a V-shaped groove 2.
次に、第2図(blに示すように、単結晶シリコン基板
1を酸化し、V字溝2を含む基板表面に、絶縁分離のた
めの二酸化シリコン膜3を形成後、該二酸化シリコン膜
3上に公知のCVD法により、膜厚0.1μm程度の窒
化シリコン膜4を形成する。Next, as shown in FIG. A silicon nitride film 4 having a thickness of about 0.1 μm is formed thereon by a known CVD method.
その後、1440℃程度の温度の溶融シリコンを、13
00℃程度に保たれたシリコン基板1上に供給し、該溶
融シリコンを基板全面に広げ、冷却することにより、窒
化シリコン膜4上に500μm程度の厚さの多結晶シリ
コン層5を形成する。After that, melted silicon at a temperature of about 1440°C was heated to 13
Polycrystalline silicon layer 5 with a thickness of about 500 μm is formed on silicon nitride film 4 by supplying the molten silicon onto silicon substrate 1 kept at about 00° C., spreading the molten silicon over the entire surface of the substrate, and cooling it.
ここで、前記窒化シリコン膜4は、V字Fn2内部まで
溶融シリコンが侵入しV字溝2内が充填される為に必要
であり、絶縁分離のための二酸化シリコン膜3上に直接
溶融シリコンを滴下したのでは、二酸化シリコン膜と溶
融シリコンのぬれ性が悪いために第3図に示すような多
結晶シリコンの未充填箇所11がV字F′s2内に発生
するからである。Here, the silicon nitride film 4 is necessary because the molten silicon penetrates into the V-shaped groove 2 and fills the inside of the V-shaped groove 2, and the molten silicon is directly deposited on the silicon dioxide film 3 for insulation isolation. This is because if the polycrystalline silicon is dropped, unfilled areas 11 of polycrystalline silicon as shown in FIG. 3 will occur in the V-shaped F's2 due to poor wettability between the silicon dioxide film and molten silicon.
その後、多結晶シリコン層5の表面を平坦な加工基準面
6まで研削した後、単結晶シリコン基板1の裏面側を、
■字Fli2の先端が露出するまで研削・研磨により除
去することにより、第2図tc+に示す誘電体分離基板
が得られろ。After that, the surface of the polycrystalline silicon layer 5 is ground to a flat processing reference surface 6, and then the back side of the single crystal silicon substrate 1 is
By removing by grinding and polishing until the tip of the letter Fli2 is exposed, a dielectric isolation substrate shown in FIG. 2 tc+ can be obtained.
(発明が解決しようとする課題)
しかしながら、上記従来の製造方法でrよ、高温の溶融
シリコンがある程度以上の質量を有する液滴状で窒化シ
リコン膜4上に供給されると、絶縁分離のための二酸化
シリコン膜3と窒化シリコン膜4との熱膨張係数の差に
基づく急激な熱応力が両方の膜の界面に生じ、窒化シリ
コン膜4が剥がれ、V字溝2内の溶融シリコンの充填が
行われないと云う問題点があった。そして、このような
未充填箇所は、第2図(clに示す誘電体分離基板の表
面にくぼみ(未充填箇所11)を形成し、後の半導体集
積回路の形成工程において、配線の段切れを起こす等に
より、半導体集積回路の製造歩留りを低下させていた。(Problem to be Solved by the Invention) However, in the above-mentioned conventional manufacturing method, when high-temperature molten silicon is supplied onto the silicon nitride film 4 in the form of droplets having a certain mass or more, insulation separation occurs. Due to the difference in thermal expansion coefficient between the silicon dioxide film 3 and the silicon nitride film 4, a sudden thermal stress is generated at the interface between the two films, causing the silicon nitride film 4 to peel off and the V-groove 2 to be filled with molten silicon. There was a problem that it was not done. In such unfilled areas, depressions (unfilled areas 11) are formed on the surface of the dielectric isolation substrate shown in FIG. As a result, the manufacturing yield of semiconductor integrated circuits has been reduced.
この発明は、以上述べた溶融シリコン供給時の窒化シリ
コン膜のはがれによる溝内の未充填と云う問題点を除去
し、溝内の充填を確実とし得る半導体基体の製造方法を
提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can eliminate the above-mentioned problem of unfilled trenches due to peeling of the silicon nitride film when supplying molten silicon and ensure filling of the trenches. shall be.
(課題を解決するための手段)
この発明では、溝を有する半導体基体の表面に二酸化シ
リコン膜を形成し、その上にシリコンオキシナイトライ
ド系のri4膜を形成し、その7[上に多結晶シリコン
層を溶融シリコンの被着により形成する。しかも、前記
シリコンオキシナイトライド系のr41#は、前記二酸
化シリコン膜に接する部分では二酸化シリコンあるいは
膜中央の部分に比して酸素組成比の高いシリコンオキシ
ナイトライド、表面部分では窒化シリコンあるいは膜中
央の部分に比して窒素組成比の高いシリコンオキシナイ
トライドからなる構成のシリコンオキシナイトライド系
のR膜と1゛ろ。(Means for Solving the Problems) In the present invention, a silicon dioxide film is formed on the surface of a semiconductor substrate having a groove, a silicon oxynitride-based ri4 film is formed on the silicon dioxide film, and a polycrystalline silicon film is formed on the silicon dioxide film. A silicon layer is formed by depositing molten silicon. Furthermore, the silicon oxynitride-based r41# is silicon oxynitride, which has a higher oxygen composition ratio than silicon dioxide or the center part of the film in the part in contact with the silicon dioxide film, and silicon nitride or silicon oxynitride in the surface part, which has a higher oxygen composition ratio than the silicon dioxide or the center part of the film. A silicon oxynitride-based R film consisting of silicon oxynitride with a higher nitrogen composition ratio than the other parts.
(作 用)
この発明では、半導体基板表面の二酸化シリコン膜上に
上述のような膜構成のシリコンオキシナイトライド系の
薄膜を形成するが、シリコンオキシナイトライド(Si
O,N、)はそのMZと窒素の組成比に応じて、二酸化
シリコンと窒化シリコンとの中間の性質を示し、上述の
膜構成とすることにより、後の工程で溶融シリコンを該
シリコンオキシナイトライド系の薄膜上に滴下した際に
、絶縁分離のための二酸化シリコン膜との界面では、そ
の二酸化シリコンと同様の熱膨張係数により膜剥がれは
生じず、表面では、窒化シリコンと同様の溶融シリコン
に対するぬれ性により、該溶融シリコンの溝内への充填
を確保する。(Function) In the present invention, a silicon oxynitride thin film having the above-mentioned film structure is formed on a silicon dioxide film on the surface of a semiconductor substrate.
O, N, ) exhibits intermediate properties between silicon dioxide and silicon nitride depending on the composition ratio of MZ and nitrogen, and by having the above-mentioned film structure, molten silicon can be converted into silicon oxynitride in a later process. When dropped onto a Ride-based thin film, the film does not peel off at the interface with the silicon dioxide film for insulation isolation due to the same coefficient of thermal expansion as silicon dioxide, and on the surface, molten silicon similar to silicon nitride does not peel off. The wettability of the molten silicon ensures that the molten silicon fills the groove.
(実施例)
以下第】図ta)ないし[d)に従い、この発明の一実
施例について誘電体分離基板を例にとり説明する。(Embodiment) Referring to Figures ta) to [d] below, an embodiment of the present invention will be described by taking a dielectric isolation substrate as an example.
才ず、第1図(a)に示すように、単結晶シリコン基板
21を酸化し、その表面に膜厚1μm程度の二酸化シリ
コンllA22を形成する。As shown in FIG. 1(a), a single-crystal silicon substrate 21 is oxidized to form a silicon dioxide film 22 with a thickness of about 1 μm on its surface.
次に、第1図(b)に示すように、ホトリソ・エツチン
グにより二酸化シリコン膜22を部分的に開孔し、残り
の二酸化シリコン膜22を保護マスクとして、単結晶シ
リコン基板21を異方性エツチングすることにより、深
さ50μm程度のv字溝23を形成する。Next, as shown in FIG. 1(b), the silicon dioxide film 22 is partially opened by photolithography and etching, and the single crystal silicon substrate 21 is anisotropically formed using the remaining silicon dioxide film 22 as a protective mask. By etching, a V-shaped groove 23 having a depth of about 50 μm is formed.
次に、第1図(clに示すように、二酸化シリコン膜2
2を除去後、再び単結晶シリコン基板21を酸化し、V
字溝23を含む基板表面に膜厚2μm程度の絶縁分離の
tこめの二酸化シリコン膜24を形成する。Next, as shown in FIG.
2, the single crystal silicon substrate 21 is oxidized again and V
A silicon dioxide film 24 having a film thickness of about 2 μm and having an insulating isolation width of T is formed on the surface of the substrate including the groove 23 .
次に、該二酸化シリコン膜24上に公知のCVD法によ
り、膜厚0.2μm程度のシリコンオキシナイトライド
(SiO,N、)系の薄膜25を二酸化シリコン膜24
側から形成表面方向に向かって、膜中の酸素に対する窒
素の組成比y / xが増加するように形成する。ここ
で、該薄膜25は、二酸化シリコン膜24に接する部分
は完全な酸化シリコンで、表面は完全な窒化シリコンで
あってもよい。Next, a silicon oxynitride (SiO,N,) thin film 25 with a thickness of about 0.2 μm is formed on the silicon dioxide film 24 by a known CVD method.
The film is formed so that the composition ratio y/x of nitrogen to oxygen in the film increases from the side toward the formation surface. Here, the portion of the thin film 25 in contact with the silicon dioxide film 24 may be made entirely of silicon oxide, and the surface thereof may be made entirely of silicon nitride.
尚、シリコンオキシナイトライド基の薄膜はS i I
(4・NH,・N20屁合ガスの熱分解により得られ、
膜形成につれてNil、/N20の混合比を増加させる
ことにより、前記膜構成のシリコンオキシナイトライド
系の4膜Z5が形成できる。又、シリコンオキシナイト
ライドはその酸素と窒素の組成比に応じて、二酸化シリ
コンと窒化シリコンとの中間の 5性質を示し、前記の
膜構成とすることにより、後の工程で溶融シリコンを該
シリコンオキシナイ)−ライド系の薄膜25上に滴下し
た際に、絶縁分離のための二酸化シリコン膜24との界
面では、その二酸化シリコンと同様の熱膨張係数により
膜剥がれは生じず、表面では、窒化シリコンと同様の溶
融シリコンに対するぬれ性により、該溶融シリコンのV
字溝23内への充填を確保する。Note that the silicon oxynitride-based thin film is S i I
(obtained by thermal decomposition of 4・NH,・N20 gas,
By increasing the mixture ratio of Nil and /N20 as the film is formed, a silicon oxynitride-based four-film Z5 having the above film structure can be formed. In addition, silicon oxynitride exhibits five properties between those of silicon dioxide and silicon nitride depending on its oxygen and nitrogen composition ratio, and by having the above-mentioned film structure, molten silicon can be converted into silicon in a later process. When dropped onto the nitride-based thin film 25, the film does not peel off at the interface with the silicon dioxide film 24 for insulation isolation due to its coefficient of thermal expansion similar to that of silicon dioxide, and the surface of the nitrided Due to the wettability of molten silicon similar to that of silicon, the V of the molten silicon
Filling of the groove 23 is ensured.
以下従来の製造方法に従い、1440℃程度の温度の溶
融シリコンを、1300〜1400℃に保たれたシリコ
ン基板21上に滴下あるいはノズルからの噴射により供
給し、該溶融シリコンを基板表面に広げ、冷却すること
により、シリコンオキシナイトライド系の薄膜25上に
550μm程度の厚さの多結晶シリコン層26を被着す
る。この時、前述のようにシリコンオキシナイトライド
系r4膜25の剥離がなく、溶融シリコンはV字溝23
内に確実に充填されろ。その後、多結晶シリコン層26
の表面を平坦な加工基準面27まで研削した後、単結晶
シリコン基板21の裏面側をV字溝23の先端が露出す
るまで研削・研磨により除去することにより、第1図(
d)に示すように単結晶シリコン島28が互いに電気的
に分離された誘電体分離基板を完成させろ。Hereinafter, according to the conventional manufacturing method, molten silicon at a temperature of about 1440°C is supplied onto the silicon substrate 21 maintained at 1300 to 1400°C by dropping or spraying from a nozzle, the molten silicon is spread over the substrate surface, and then cooled. As a result, a polycrystalline silicon layer 26 with a thickness of about 550 μm is deposited on the silicon oxynitride thin film 25. At this time, as mentioned above, the silicon oxynitride-based R4 film 25 does not peel off, and the molten silicon remains in the V-shaped groove 25.
Make sure it is filled inside. After that, the polycrystalline silicon layer 26
After grinding the surface to a flat processing reference surface 27, the back side of the single crystal silicon substrate 21 is removed by grinding and polishing until the tip of the V-shaped groove 23 is exposed.
Complete a dielectric isolation substrate in which single crystal silicon islands 28 are electrically isolated from each other as shown in d).
尚、上記実施例では誘電体分S基板をとり上げたが、こ
の発明は、その他の同様の半導体基体の製造方法にも適
用できる。Although the above embodiment deals with a dielectric S substrate, the present invention can also be applied to other similar methods of manufacturing semiconductor substrates.
(発明の効果)
以上詳細に説明したようにこの発明によれば、溶融シリ
コンの溝内の充填を確保するためにシリコンオキシナイ
トライド系のr11II!11特に半導体基板表面の二
酸化シリコン膜と接する部分では二酸化シリコンあるい
は膜中央の部分に比して酸素組成比の高いシリコンオキ
シナイトライド、表面部分では窒化シリコンあるいは膜
中央の部分に比して窒素組成比の高いシリコンオキシナ
イトライドからなる構成のシリコンオキシナイトライド
系の薄膜を形成するようにしlコので、前記二酸化シリ
コン膜との熱膨張係数の差に基づく高温溶融シリコン供
給時の充填確保用r4膜の剥がれを防止ずろことができ
、溶融シリコンの溝内の充填を確実なものとすることが
できる。したがって、例えば誘電体分離基板において表
面のくぼみの発生を防止でき、集積回路を形成した際に
配線が前記くぼみにより段切れを起こすことを防止でき
、半導体集積回路の製造歩留りを真めろことができろ。(Effects of the Invention) As described above in detail, according to the present invention, silicon oxynitride-based r11II! 11 Particularly, in the area in contact with the silicon dioxide film on the surface of the semiconductor substrate, silicon oxynitride has a higher oxygen composition ratio than that of silicon dioxide or the central part of the film, and in the surface part, silicon oxynitride has a higher oxygen composition ratio than that of silicon nitride or the central part of the film. In order to form a silicon oxynitride-based thin film composed of silicon oxynitride with a high ratio, a silicon oxynitride film is used to ensure filling when supplying high-temperature molten silicon based on the difference in thermal expansion coefficient with the silicon dioxide film. It is possible to prevent the film from peeling off and to ensure that the grooves are filled with molten silicon. Therefore, for example, it is possible to prevent the occurrence of depressions on the surface of a dielectric isolation substrate, and when an integrated circuit is formed, it is possible to prevent wiring from breaking due to the depressions, thereby improving the manufacturing yield of semiconductor integrated circuits. You can do it.
第1図はこの発明の半導体基体の製造方法の一実施例を
示す工程断面図、第2図は従来の誘電体分離基板の製造
方法を示す工程断面図、第3図は従来の方法において窒
化シリコン膜が無い場合に生じろ溶融シリコンの溝内の
未充填を示す断面図である。
21・・単結晶シリコン基板、23・ V字溝、24・
・二酸化シリコン膜、25・・シリコンオキシナイトラ
イド系の#FJ、2s・・・多結晶シリコン層。
本発明一実施例の製造工程断面図
従来の製造工程断面図FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor substrate of the present invention, FIG. 2 is a process sectional view showing a conventional method for manufacturing a dielectric isolation substrate, and FIG. 3 is a nitriding process in the conventional method. FIG. 3 is a cross-sectional view illustrating unfilled grooves of molten silicon that would occur in the absence of a silicon film. 21. Single crystal silicon substrate, 23. V-shaped groove, 24.
- Silicon dioxide film, 25...Silicon oxynitride type #FJ, 2s...Polycrystalline silicon layer. A sectional view of a manufacturing process according to an embodiment of the present invention A sectional view of a conventional manufacturing process
Claims (1)
面に二酸化シリコン膜を形成する工程と、(b)該二酸
化シリコン膜上に、該二酸化シリコン膜に接する部分で
は二酸化シリコンあるいは膜中央の部分に比して酸素組
成比の高いシリコンオキシナイトライド、表面部分では
窒化シリコンあるいは膜中央の部分に比して窒素組成比
の高いシリコンオキシナイトライドからなる構成のシリ
コンオキシナイトライド系の薄膜を形成する工程と、(
c)該薄膜上に、溶融シリコンの被着固化により多結晶
シリコン層を形成する工程とを具備してなる半導体基体
の製造方法。(a) forming a silicon dioxide film on the surface of the semiconductor substrate including the inside of the groove of a semiconductor substrate having a groove; A silicon oxynitride-based thin film consisting of silicon oxynitride, which has a higher oxygen composition ratio than the central part, and silicon nitride in the surface part, or silicon oxynitride, which has a higher nitrogen composition ratio than the central part of the film. The process of forming (
c) forming a polycrystalline silicon layer on the thin film by depositing and solidifying molten silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28873588A JPH02135754A (en) | 1988-11-17 | 1988-11-17 | Manufacture of semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28873588A JPH02135754A (en) | 1988-11-17 | 1988-11-17 | Manufacture of semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02135754A true JPH02135754A (en) | 1990-05-24 |
Family
ID=17734011
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28873588A Pending JPH02135754A (en) | 1988-11-17 | 1988-11-17 | Manufacture of semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02135754A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7202568B2 (en) * | 1998-06-26 | 2007-04-10 | Intel Corporation | Semiconductor passivation deposition process for interfacial adhesion |
CN103489821A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for filling groove with high aspect ratio |
-
1988
- 1988-11-17 JP JP28873588A patent/JPH02135754A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7202568B2 (en) * | 1998-06-26 | 2007-04-10 | Intel Corporation | Semiconductor passivation deposition process for interfacial adhesion |
CN103489821A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for filling groove with high aspect ratio |
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