JPH02134860A - Manufacture of large-scale integrated circuit - Google Patents

Manufacture of large-scale integrated circuit

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Publication number
JPH02134860A
JPH02134860A JP63289211A JP28921188A JPH02134860A JP H02134860 A JPH02134860 A JP H02134860A JP 63289211 A JP63289211 A JP 63289211A JP 28921188 A JP28921188 A JP 28921188A JP H02134860 A JPH02134860 A JP H02134860A
Authority
JP
Japan
Prior art keywords
thin film
semiconductor
semiconductor thin
substrate
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63289211A
Other languages
Japanese (ja)
Other versions
JP2734025B2 (en
Inventor
Shunji Nakamura
俊二 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63289211A priority Critical patent/JP2734025B2/en
Publication of JPH02134860A publication Critical patent/JPH02134860A/en
Application granted granted Critical
Publication of JP2734025B2 publication Critical patent/JP2734025B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To provide a three-dimensional large-scale integrated circuit with high integration, high reliability, high yield, and low cost by bonding a semiconductor chip wherein an integrated circuit is formed on a second semiconductor thin film formed on a semiconductor substrate onto an insulating substrate with the thin film side thereof down, removing the semiconductor substrate, and likewise superimposing a semiconductor thin film piece on the resulting semiconductor chip. CONSTITUTION:A semiconductor chip 101 wherein a second semiconductor thin film 2 is formed on a semiconductor substrate 1 on which thin film an integrated circuit including a diffusion area 4 for pads is formed, and the surface of the resulting sample is covered with a coating insulating film 7, is bonded to an insulating substrate 8 with the thin film 2 side thereof down, and the substrate 1 is removed. Then, an upper stage semiconductor chip is bonded, with the semiconductor thin film side down, onto an area of the rear surface of the remaining fixed thin film piece 2 where there is no diffusion area 4 for pads, and the substrate is removed to leave and fix the upper stage semiconductor thin film piece. Further, there is formed on the resulting thin film piece a second insulating film 10 having an opening for exposing the rear surfaces of the diffusion areas 4 for pads of the lower and upper stage semiconductor thin film piece 2, through an opening of which a conductor film wiring 11 for connecting between the diffusion areas 4 for pads of the upper and lower stage semiconductor thin film pieces 2 is formed.

Description

【発明の詳細な説明】 〔目　次〕 ］概要 産業上の利用分野 従来の技術 発明が解決しようとする課題 課題を解決するための手段 作用 実施例 一実施例の工程断面図（第２図） 一実施例の模式斜視図（第３図） チップ形成方法の工程断面図（第４図）他の実施例の斜
視図及び断面図（第５図）発明の効果 〔概　要〕 本発明は３次元構造を有する大規模集積回路の製造方法
に関し、 高集積度、高信頼、高歩留り、低コストを存する大規模
集積回路の提供を目的とし、 第１の半導体基板上に第２の半導体薄膜が形成され、該
半導体薄膜に該半導体薄膜の上面から底面に達するパッ
ド用拡散領域を選択的に有する集積回路が形成され、表
面が被覆絶縁膜で覆われ、該集積回路の特性選別が完了
してなる半導体チップを用い、下段になる上記半導体チ
ップを絶縁性基板上に半導体薄膜側を下にして接着し、
該下段の半導体チップの半導体基板を除去した後、絶縁
性基板上に残留固着された下段の半導体薄膜片の裏面の
パッド用拡散領域が配設さ゛れていない領域上に、上段
の半導体チップを半導体薄膜側を下にして接着し、該上
段チップの半導体基板を除去して下段の半導体薄膜片裏
面のパッド用拡散領域が配設されていない領域上に上段
の半導体薄膜片を裏面を表出した状態で残留固着せしめ
、該基板上に下段及び上段の半導体薄膜片におけるパッ
ド用拡散領域の裏面を表出する第２の開口を有する第２
の絶縁膜を形成し、該第２の開口を通じ上段と下段の半
導体薄膜片のパッド用拡散領域間を接続する導電膜配線
を形成する工程を含んで構成される。[Detailed Description of the Invention] [Table of Contents] ] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example 1 Process sectional view of the example (Figure 2) Schematic perspective view of one embodiment (Fig. 3) Process sectional view of chip forming method (Fig. 4) Perspective view and sectional view of another embodiment (Fig. 5) Effects of the invention [Summary] The present invention has 3 Regarding a method for manufacturing a large-scale integrated circuit having a dimensional structure, the purpose is to provide a large-scale integrated circuit having a high degree of integration, high reliability, high yield, and low cost, and a second semiconductor thin film is formed on a first semiconductor substrate. an integrated circuit is formed in the semiconductor thin film, selectively having a pad diffusion region extending from the top surface to the bottom surface of the semiconductor thin film, the surface is covered with a covering insulating film, and characteristic selection of the integrated circuit is completed; The lower semiconductor chip is bonded onto an insulating substrate with the semiconductor thin film side facing down,
After removing the semiconductor substrate of the lower semiconductor chip, the upper semiconductor chip is placed on the area where the pad diffusion region is not provided on the back side of the lower semiconductor thin film piece that remains fixed on the insulating substrate. The semiconductor substrate of the upper chip was removed, and the back surface of the upper semiconductor thin film piece was exposed on the area where the pad diffusion region was not provided on the back side of the lower semiconductor thin film piece. a second opening having a second opening exposing the back surface of the pad diffusion region in the lower and upper semiconductor thin film pieces on the substrate;
The method includes the steps of forming an insulating film, and forming a conductive film interconnection connecting between the pad diffusion regions of the upper and lower semiconductor thin film pieces through the second opening.

〔産業上の利用分野〕[Industrial application field]

本発明は３次元構造を有する大規模集積回路の製造方法
に関する。The present invention relates to a method for manufacturing large-scale integrated circuits having three-dimensional structures.

現在の半導体集積回路は、半導体基板のほぼ表面部に横
方向の拡がりを持って２次元的に構成されている。Current semiconductor integrated circuits are two-dimensionally constructed with a lateral extension substantially on the surface of a semiconductor substrate.

そのため微細加工技術の限界によって集積度にも自ずか
ら限界を生じており、この限界を打破して更に高集積度
を達成するために、一つの手段として３次元集積回路の
開発が進められている。Therefore, there is a natural limit to the degree of integration due to the limitations of microfabrication technology, and in order to overcome this limit and achieve even higher degrees of integration, three-dimensional integrated circuits are being developed as one means.

〔従来の技術〕[Conventional technology]

３次元集積回路を形成するための従来技術の一つに、集
積回路の形成された半導体基体上の絶縁膜上に、多結晶
シリコン（Ｓｉ）層を堆積し、レーザ光照射等により該
多結晶ＳｉＮを溶融、再結晶化して単結晶Ｓｉ層を形成
し、該単結晶Ｓｉ層を用いて集積回路の形成を行い、下
部の集積回路と上部の集積回路間を配線接続して構成す
る所謂３０１（ｓｉｌｉｃｏｎ　ｏｎ　１ｎｓｕｌａｔ
ｏｒ）技術によるものがある。One of the conventional techniques for forming a three-dimensional integrated circuit is to deposit a polycrystalline silicon (Si) layer on an insulating film on a semiconductor substrate on which an integrated circuit is formed, and then remove the polycrystalline silicon (Si) layer by irradiation with a laser beam or the like. The so-called 301 process involves melting and recrystallizing SiN to form a single-crystal Si layer, forming an integrated circuit using the single-crystal Si layer, and connecting the lower integrated circuit and the upper integrated circuit with wiring. (silicon on 1nsulat
or) It depends on technology.

しかしこの方法には、下記の（ａ）〜（ｄ）に示すよう
な問題点がある。However, this method has problems as shown in (a) to (d) below.

（ａ）単結晶Ｓｉ層の結晶の完全性が得られず、素子性
能が劣る。(a) The crystal integrity of the single-crystal Si layer cannot be obtained, resulting in poor device performance.

■）歩留りが層を重ねる毎にその積となるので、３次元
回路としての歩留りが大幅に低下する。(2) Since the yield is the product of each layer, the yield as a three-dimensional circuit decreases significantly.

（Ｃ）　１層ずつ層を積層して形成して行くために層数
に比例して工程数が増すので、製造のコストや手番が増
大する。(C) The number of steps increases in proportion to the number of layers because the layers are formed by laminating one layer at a time, resulting in an increase in manufacturing costs and steps.

（ｄ）各層の単結晶層について拡散層の形成、絶縁膜の
形成等の熱処理が必要なため、下層程全熱処理量が多く
なって素子特性の変動を生ずる。(d) Since heat treatment such as formation of a diffusion layer and an insulating film is required for each single crystal layer, the total amount of heat treatment increases as the layer goes lower, causing variations in device characteristics.

そこで上記Ｓｏｌ技術による問題点を除去するために提
供されたのは、第６図に示すように、集積回路の形成さ
れた通常の半導体チップ５１．５２．５３等を配線基板
５０上に積重ねて固着し、各チップに形成されている集
積回路間を配線接続して３次元構成を有する大規模集積
回路を形成する方法であった。Therefore, in order to eliminate the problems caused by the above-mentioned Sol technology, as shown in FIG. This was a method of forming a large-scale integrated circuit having a three-dimensional structure by bonding the integrated circuits together and connecting the integrated circuits formed on each chip with wiring.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし上記通常の半導体チップの積重ねによる従来構造
においては、同図に示すように、半導体チップ５１．５
２．５３等の厚さによる段差り６、ｈ２、ｈ３等が４０
０〜６００μｍ程度あるためにチップ相互間を薄膜状の
金属配線で接続することは、ステップカバレージ性の不
足から断線を生ずることによって不可能であり、そのた
め図示のように絶縁性基板（配線基板）５０及び半導体
チップ５１．５２．５３等のポンディングパッド５４Ａ
　、　５４Ｂ　、　５４Ｃ、５４０等の相互間を金等の
ボンディングワイヤ５５で接続して３次元構造を有する
大規模集積回路が構成されていた。However, in the conventional structure in which the normal semiconductor chips are stacked, as shown in the same figure, the semiconductor chips 51.5
2.53 steps due to thickness 6, h2, h3 etc. are 40
Since the thickness is about 0 to 600 μm, it is impossible to connect chips with thin film metal wiring because the step coverage is insufficient and disconnection occurs. Therefore, as shown in the figure, an insulating substrate (wiring board) 50 and semiconductor chips 51, 52, 53, etc. bonding pads 54A
, 54B, 54C, 540, etc., are connected to each other by bonding wires 55 made of gold or the like to form a large-scale integrated circuit having a three-dimensional structure.

従って、変形、倒れ等によるボンディングワイヤ相互間
の接触を避けるため、配線密度を余り高めることができ
ず高集積化が阻害され、またボンディング個所の増大に
よって歩留り、信頼性の低下、及び製造コストの増大を
招くという問題があった。Therefore, in order to avoid contact between the bonding wires due to deformation, falling, etc., it is not possible to increase the wiring density much, which hinders high integration.In addition, the increase in the number of bonding locations reduces yield, reliability, and increases manufacturing costs. There was a problem in that it caused an increase in the amount of water.

そこで本発明は、高集積度、高信頼、高歩留り、低コス
トを有する３次元構造の大規模集積回路の提供を目的と
する。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a large-scale integrated circuit with a three-dimensional structure that has a high degree of integration, high reliability, high yield, and low cost.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は、第１の半導体基板と、該半導体基板上にエ
ピタキシャル成長させた該第１の半導体とエツチングの
選択性を有する第２の半導体薄膜と、該第２の半導体薄
膜の表面部に能動素子が形成されてなる素子領域と、該
第２の半導体薄膜に選択的に該第２の半導体薄膜の表面
から裏面に達する深さに形成されたパッド用拡散領域と
、該第２の半導体薄膜上に形成された第１の絶縁膜と、
該第１の絶縁膜上に形成され該能動素子とパッド用拡散
領域上の所定位置に対応する第１の開口を有する第１の
絶縁膜と、該第１の絶縁膜上に形成され該第１の開口を
通じて該能動素子間及び該能動素子と該パッド用拡散領
域間を接続して集積回路を構成する第１の導電膜配線と
を有し、該集積回路の選別試験を完了してなる同種若し
くは異種の複数の半導体チップを用い、下段になる該半
導体チップを、該第１の半導体に対してエツチングの選
択性を有する絶縁性基板上に、該第２の半導体薄膜側を
対向させて、直に若しくは該第１の半導体とエツチング
の選択性を有する絶縁物質を介し接着する工程と、エツ
チング手段により該下段の半導体チップの第１の半導体
基板を選択的に除去して、該絶縁性基板上に該下段の半
導体チップの第２の半導体薄膜片を裏面を表出した状態
で固着残留せしめる工程と、該下段の第２の半導体薄膜
片裏面の該パッド用拡散領域が配設されていない領域上
に、該下段と同種若しくは異種の上段になる該半導体チ
ップを、該第２の半導体薄膜側を対向させて、該第１の
半導体とエツチングの選択性を有する絶縁物質を介し接
着する工程と、エツチング手段により該上段の半導体チ
ップの半導体基板を選択的に除去して、該下段の第２の
半導体薄膜裏面の該パッド用拡散領域が配設されていな
い領域の上部に、上段の第２の半導体薄膜片を裏面を表
出した状態で固着残留せしめる工程と、該第２の半導体
薄膜片が重着された第２の半導体薄膜片積層体及び該絶
縁性基板上に第２の絶縁膜を形成する工程と、該第２の
絶縁膜に、該下段及び上段の第２の半導体薄膜片におけ
るパッド用拡散領域の裏面を　個々に表出する複数の第
２の開口を形成する工程と、該複数の第２の開口を通じ
、該上段の第２の半導体薄膜のパッド用拡散領域と該下
段の第２の半導体薄膜のパッド用拡散領域とを相互に接
続する第２の導電膜配線を形成する工程とを有する本発
明による大規模集積回路の製造方法によって解決される
。The above problem consists of a first semiconductor substrate, a second semiconductor thin film that is epitaxially grown on the semiconductor substrate and has etching selectivity with respect to the first semiconductor, and an active element on the surface of the second semiconductor thin film. a pad diffusion region selectively formed in the second semiconductor thin film to a depth reaching from the front surface to the back surface of the second semiconductor thin film; a first insulating film formed on;
a first insulating film formed on the first insulating film and having a first opening corresponding to a predetermined position on the active element and the pad diffusion region; a first conductive film wiring that connects the active elements and the active element and the pad diffusion region through the first opening to form an integrated circuit, and has undergone a screening test for the integrated circuit. A plurality of semiconductor chips of the same type or different types are used, and the lower semiconductor chip is placed on an insulating substrate having etching selectivity with respect to the first semiconductor, with the second semiconductor thin film side facing the semiconductor chip. , a step of adhering the first semiconductor directly or through an insulating material having etching selectivity, and selectively removing the first semiconductor substrate of the lower semiconductor chip by etching means to remove the first semiconductor substrate of the lower semiconductor chip; A step of fixing and remaining a second semiconductor thin film piece of the lower semiconductor chip on the substrate with its back side exposed, and a diffusion region for the pad on the back side of the lower second semiconductor thin film piece are provided. The semiconductor chip to be the upper layer, which is the same type or different from the lower layer, is bonded to the first semiconductor on an area where there is no etching, with the second semiconductor thin film side facing the first semiconductor through an insulating material having etching selectivity. In this step, the semiconductor substrate of the upper semiconductor chip is selectively removed by etching means, and the upper semiconductor chip is etched onto the upper part of the region where the pad diffusion region is not provided on the back surface of the lower second semiconductor thin film. a step of fixing and remaining a second semiconductor thin film piece with its back side exposed; a step of forming an insulating film; and a step of forming a plurality of second openings in the second insulating film to individually expose the back surfaces of the pad diffusion regions in the lower and upper second semiconductor thin film pieces. and a second conductive film wiring interconnecting the pad diffusion region of the upper second semiconductor thin film and the pad diffusion region of the lower second semiconductor thin film through the plurality of second openings. The present invention provides a method for manufacturing large-scale integrated circuits, comprising the steps of: forming a large-scale integrated circuit;

（作　用） 第１図（ａ）〜（Ｃ）　−１及び（Ｃ）　−２は本発明
の原理を示す工程断面図である。(Function) FIGS. 1(a) to (C)-1 and (C)-2 are process sectional views showing the principle of the present invention.

即ち本発明は第１図（ａ）に示すように、例えばＳｉ基
板ｌ上にエピタキシャル成長させた炭化珪素（ＳｉＣ）
　薄膜２の素子領域３上に、該素子領域３に形成された
トランジスタ等の能動素子を用い第１の金属（導電）膜
配線（チップ内配線）６によって集積回路が形成され、
該ＳｉＣ薄膜２の一部領域例えば該素子領域３の周辺に
形成されたＳｉｃ　ａ膜２の底面に達するパッド用拡散
領域４上に前記金属膜配線６が導出接続され、該集積回
路の試験、選別を終わった同種または異種の複数の半導
体チップ１０１が用いられる。なお図において、５は層
間絶縁膜、７は被覆絶縁膜を示す。That is, the present invention, as shown in FIG.
An integrated circuit is formed on the element region 3 of the thin film 2 by first metal (conductive) film wiring (in-chip wiring) 6 using active elements such as transistors formed in the element region 3,
The metal film wiring 6 is led out and connected onto a pad diffusion region 4 that reaches the bottom surface of the SiCa film 2 formed around a part of the SiC thin film 2, for example, the element region 3, and is used for testing the integrated circuit. A plurality of semiconductor chips 101 of the same type or different types that have been sorted are used. In the figure, 5 indicates an interlayer insulating film, and 7 indicates a covering insulating film.

そして第１回部）に示すように、この半導体チップ１０
１を、絶縁性基板８上に、ＳｉＣ薄膜２側を対向させて
接着剤９Ａにより接着した後、鎖線で示すＳｉ基板１を
選択的にエツチング除去して絶縁性基板８上に裏面を表
出するＳｉｃ　薄膜片２Ａ　（前記ＳｉＣ薄膜２に対応
）を固着残留せしめる。この際上記ＳｉＣ薄膜片２の裏
面にはパッド用拡散領域４の底面が露出する。As shown in Part 1), this semiconductor chip 10
1 on an insulating substrate 8 with the SiC thin film 2 side facing each other using an adhesive 9A, and then selectively etching away the Si substrate 1 shown by the chain line to expose the back surface on the insulating substrate 8. The SiC thin film piece 2A (corresponding to the SiC thin film 2) is left fixed. At this time, the bottom surface of the pad diffusion region 4 is exposed on the back surface of the SiC thin film piece 2.

以後同様な方法によって、接着剤９Ｂ、９Ｃを介し、下
段のＳｉＣ薄膜片２Ａ裏面のパッド用拡散領域４が形成
されていない領域即ち素子領域に対応する領域上に、同
種または異種の半導体チップに形成されている上段のＳ
ｉＣ薄膜片２Ｂ、２Ｃ等を、表面を下にして、第１図（
Ｃ）　−１或いは第１図（Ｃ）　−２のように積み重ね
て接着し、この基板上に、各々のＳｉＣ薄膜片２Ａ、２
Ｂ、２０等のパッド用拡散領域４の底面を表出する開口
を有する絶縁膜１０を形成し、この開口を通じて各々の
ＳｉＣ薄膜片２Ａ、２Ｂ、２０等に形成されている集積
回路を第２の金属（導電）膜配線（チップ外配線）１１
で相互に接続することにより３次元構造の大規模集積回
路を構成する。Thereafter, using the same method, a semiconductor chip of the same or different type is attached to the back surface of the lower SiC thin film piece 2A on the region where the pad diffusion region 4 is not formed, that is, the region corresponding to the element region. The upper S formed
Place the iC thin film pieces 2B, 2C, etc. with their surfaces facing down in Figure 1 (
C)-1 or FIG. 1(C)-2, each SiC thin film piece 2A, 2
An insulating film 10 having an opening exposing the bottom surface of the pad diffusion region 4 such as B, 20, etc. is formed, and the integrated circuit formed on each SiC thin film piece 2A, 2B, 20, etc. is transferred to the second layer through this opening. Metal (conductive) film wiring (outside chip wiring) 11
By interconnecting them, a large-scale integrated circuit with a three-dimensional structure is constructed.

なお、第１図（ｂ）、（Ｃ）　−１、（Ｃ）　−２にお
いては、層間絶縁膜５、第１の金属膜配線６は省略する
。Note that in FIGS. 1(b), (C)-1, and (C)-2, the interlayer insulating film 5 and the first metal film wiring 6 are omitted.

上記構成において、第２半導体薄膜片即ちＳｉＣ薄膜片
２八、２Ｂ、２０等の厚さは０．０５〜０．５　ｐｍ程
度で形成することが充分に可能である。In the above structure, it is fully possible to form the second semiconductor thin film pieces, ie, the SiC thin film pieces 28, 2B, 20, etc., with a thickness of about 0.05 to 0.5 pm.

そのため、絶縁性基板８と１段目のＳｉＣ薄膜片２へ上
面との段差ｈＡ、１段目のＳｉＣ薄膜片２Ａの上面と２
段目のＳｉｃ　ＦｉＩ膜片２Ｂ上面との段差ｈＢ、２段
目のＳｉＣ薄膜片２Ｂの上面と３段目のＳｉＣ薄膜片２
Ｃの上面との段差ｈＣ等は総て金属膜配線６、層間絶縁
膜５、接着剤９八或いは９Ｂ或いは９０等を含めても０
．５〜１．５μｍ程度の低い段差になる。この段差は、
金属薄膜形成技術におけるステップカバレージ性を充分
に満足できる値である。Therefore, there is a step hA between the top surface of the insulating substrate 8 and the first SiC thin film piece 2, and a difference hA between the top surface of the first SiC thin film piece 2A and the top surface of the first SiC thin film piece 2A.
Level difference hB between the top surface of the SiC FiI film piece 2B on the second stage and the top surface of the SiC thin film piece 2B on the second stage and the SiC thin film piece 2 on the third stage.
The height difference hC with the top surface of C is all 0 including the metal film wiring 6, interlayer insulating film 5, adhesive 98 or 9B or 90, etc.
．． This results in a low level difference of about 5 to 1.5 μm. This step is
This is a value that fully satisfies step coverage in metal thin film forming technology.

従って本発明の方法によれば、３次元構造の大規模集積
回路の層間の接続を導電膜配線を用いリソグラフィ技術
により形成することが可能になり、これによって、積層
チップの層間接続の配線密度が向上できて高集積化が可
能になり、且つボンディング個所が減少して歩留り、信
頼性の向上、及び製造コストの低減が図れる。Therefore, according to the method of the present invention, it becomes possible to form connections between layers of a large-scale integrated circuit with a three-dimensional structure using conductive film wiring using lithography technology, thereby increasing the wiring density of the connections between layers of stacked chips. This makes it possible to achieve high integration, and to reduce the number of bonding locations, thereby improving yield, reliability, and reducing manufacturing costs.

〔実施例］ 以下本発明を、図示実施例により具体的に説明する。〔Example] The present invention will be specifically explained below with reference to illustrated embodiments.

第２図（ａ）〜（ｄ）は本発明の一実施例の工程断面図
、第３図は同実施例の模式斜視図、第４図（ａ）〜（ｄ
）は本発明に用いる半導体チップの形成工程の一実施例
を示す工程断面図、第５図は本発明の他の実施例の模式
図で、（ａ）は透視平面図、（ｂ）はＡ−Ａ矢視断面図
である。FIGS. 2(a) to (d) are process sectional views of an embodiment of the present invention, FIG. 3 is a schematic perspective view of the same embodiment, and FIGS. 4(a) to (d).
) is a process sectional view showing one embodiment of the process of forming a semiconductor chip used in the present invention, and FIG. 5 is a schematic diagram of another embodiment of the present invention, (a) is a perspective plan view, and (b) is A. -A cross-sectional view.

全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.

本発明に係る３次元構造の大規模集積回路の製造方法に
用いる半導体チップは、例えば以下に要部を示す工程断
面図第４図（ａ）〜（ｄ）を参照して説明する方法によ
り形成される。The semiconductor chip used in the method for manufacturing a large-scale integrated circuit with a three-dimensional structure according to the present invention is formed, for example, by the method described below with reference to process cross-sectional diagrams 4(a) to 4(d) showing important parts. be done.

第４図（ａ）参照 即ち、通常の方法、例えば５ｉＨＣ１ｉ　（）リクロロ
シラン）と　ＣＪａ　（プロパン）とＰＨ１（フォスフ
イン）の混合ガス中で、第１の半導体基板例えハ４００
〜６００μｍ程度の厚さを有する単結晶のＳｉ基板ｌを
１０００°Ｃ程度に加熱して、該Ｓｉ基板１上にＳｉと
エツチングの選択性を有する厚さｔ　＝２０００人程度
の第２の半導体薄膜即ちｎ型のＳｉＣａ膜２をエピタキ
シャル成長させる。Referring to FIG. 4(a), the first semiconductor substrate (e.g., 400 g
A single-crystal Si substrate l having a thickness of ~600 μm is heated to about 1000°C, and a second semiconductor having a thickness t = about 2000 and having selectivity of etching with Si is formed on the Si substrate 1. A thin film, that is, an n-type SiCa film 2, is epitaxially grown.

第４図ら）参照 次いで通常の集積回路の製造におけるのと同様の方法を
用いて、上記５ｔｃｌ膜２の素子領域３には例えばｐ・
型のソース／ドレイン領域１２Ａ　、１２Ｂとゲート絶
縁膜１３及びポリＳｉのゲート電極１４からなるＭＩＳ
Ｉ−ランジスタ（Ｔｒ）等の能動素子を、また、ＳｉＣ
薄膜２の一部領域例えば素子領域周辺に設けるパッド領
域１５にはＳｉＣ薄膜２の底面に達するｐ°型のパッド
用拡散領域４等を形成する。Referring to FIG. 4 et al.) Next, using a method similar to that used in the manufacture of ordinary integrated circuits, the element region 3 of the 5TCL film 2 is formed, for example, with p.
An MIS consisting of type source/drain regions 12A and 12B, a gate insulating film 13, and a poly-Si gate electrode 14.
Active elements such as I-transistors (Tr) and SiC
In a part of the thin film 2, for example, a pad region 15 provided around the element region, a p° type pad diffusion region 4 reaching the bottom surface of the SiC thin film 2 is formed.

第４図（Ｃ）参照 次いで上記チップ領域上に、ＰＳＧ等よりなる厚さ３０
００人程度０層間絶縁膜５を形成し、該層間絶縁膜５に
トランジスタＴｒのソース／ドレインＳＮ域１２Ａ　、
１２Ｂ等及びパッド用拡散領域４等の上面を表出するコ
ンタクト窓を形成し、該層間絶縁膜５上に通常の方法に
より前記コンタクト窓を介しソース／ドレイン領域１２
Ａ及び図示されないゲート開孔領域とパッド用拡散領域
４、及びソース／ドレイン領域１２Ｂ及び図示されない
ゲート開孔領域と図示されないトランジスタのソース／
ドレイン及びゲート領域或いはパッド用拡散領域等を相
互に接続する例えば厚さ０．５μｍ程度のアルミニウム
（ＡＩ）よりなるチップ内配線即ち第１の金属膜配線６
を形成する。Referring to FIG. 4(C), a thickness of 30 mm made of PSG or the like is then placed on the chip area.
An interlayer insulating film 5 is formed, and the source/drain SN region 12A of the transistor Tr is formed on the interlayer insulating film 5.
A contact window is formed to expose the upper surfaces of the pad diffusion region 4 and the like, and the source/drain region 12 is formed on the interlayer insulating film 5 through the contact window by a conventional method.
A, a gate opening region (not shown), a pad diffusion region 4, a source/drain region 12B, a gate opening region (not shown), and a transistor source/drain region (not shown).
In-chip wiring, ie, first metal film wiring 6, made of aluminum (AI) with a thickness of about 0.5 μm, for example, interconnecting drain and gate regions or pad diffusion regions, etc.
form.

第４図（ｄ） 次いで通常上記チップ領域上に厚さ１μｍ程度のＰＳＧ
等よりなるパッシベーション用の被覆絶縁膜７を形成し
、更に該被覆絶縁膜７の、各々のチップ領域におけるパ
ッド用拡散領域４に対応する位置に該領域上の第１の金
属膜配線６を表出する試験用開口１６を形成し、該試験
用開口１６内に表出する第１の金属膜配線６及び図示さ
れない他領域の試験用開口内に表出する第１の金属膜配
線に、試験装置のプローブを接触させて該チップ領域に
形成されている集積回路の特性を試験し、正常な集積回
路が形成されているチップ領域に識別マークを付す。そ
して該基板を通常のダイシング手段によりチップ単位に
分割し、正常な集積回路が形成されている良品チップを
保管する。FIG. 4(d) Next, PSG with a thickness of about 1 μm is usually placed on the chip area.
A covering insulating film 7 for passivation is formed, and a first metal film wiring 6 is formed on the covering insulating film 7 at a position corresponding to the pad diffusion region 4 in each chip region. A test opening 16 is formed to expose the first metal film wiring 6 exposed in the test opening 16 and the first metal film wiring exposed in the test opening in another region not shown. The characteristics of the integrated circuit formed in the chip area are tested by contacting the probe of the device, and an identification mark is attached to the chip area where a normal integrated circuit is formed. Then, the substrate is divided into chips by ordinary dicing means, and good chips on which normal integrated circuits are formed are stored.

本発明の方法に係る一実施例においては、下層のチップ
領域の直上部に上層のチップ領域が積層される構造なの
で、上、下層間の配線が可能なように、上層のチップが
、パッド用拡散領域の上部を残して下層のチップ上を覆
うように、順次小型になる複数種類の大きさのチップ１
０１Ａ、ｌ０ＩＢ、１ＯＩＣ等が用意される。In one embodiment of the method of the present invention, since the upper layer chip area is stacked directly above the lower layer chip area, the upper layer chip is stacked for pads so that wiring between the upper and lower layers is possible. Chips 1 of multiple sizes that gradually become smaller so as to cover the lower layer chips while leaving the upper part of the diffusion region
01A, 10IB, 1OIC, etc. are prepared.

そして３次元構造の大規模集積回路は、以下に第２図（
ａ）〜（ｄ）を参照して説明する。なお第２図において
はチップ内で集積回路を構成している前記ソース／ドレ
イン領域１２八、１２Ｂ　、ゲート酸化膜１３、ゲート
電極１４、層間絶縁膜５、第１の金属膜配線６等は省略
する。A large-scale integrated circuit with a three-dimensional structure is shown in Figure 2 (
This will be explained with reference to a) to (d). Note that in FIG. 2, the source/drain regions 128, 12B, gate oxide film 13, gate electrode 14, interlayer insulating film 5, first metal film wiring 6, etc. that constitute the integrated circuit within the chip are omitted. do.

第２図（ａ）参照 先ず、パンケージ等を構成するセラミック等の絶縁性基
板８（配線基板の場合もある）上に硼素・燐珪酸ガラス
（ＢＰＳＧ）等よりなる絶縁性の接着剤９＾を厚さ１０
００人程度０皮膜状に形成した後、その上にＩＮ目にな
る半導体チップ１０１ＡをＳｉＣ”７Ｎ膜チツプ２Ａ側
を対向させて載置し、４００°Ｃ程度に加熱することに
よって固着する。そして鎖線で図示しである上記半導体
チップｌ０ＩＡのＳｉ基板ＩＡの部分を、苛性カリ液或
いは弗硝酸液を用いて選択的にエツチング除去する。図
中、７はチップの表面を保護する被覆絶縁膜を示す。Refer to FIG. 2(a) First, an insulating adhesive 9 made of boron phosphosilicate glass (BPSG) or the like is applied onto an insulating substrate 8 (sometimes a wiring board) made of ceramic or the like that constitutes a pan cage or the like. thickness 10
After forming a film of about 0.00000000000000000000000000000000000000000000000000000 C, a semiconductor chip 101A serving as the IN-th layer is placed thereon with the SiC''7N film chip 2A facing each other, and fixed by heating to about 400°C. The portion of the Si substrate IA of the semiconductor chip 10IA shown by the chain line is selectively etched away using caustic potash solution or fluoronitric acid solution. In the figure, 7 indicates a covering insulating film that protects the surface of the chip. .

第２図（ｂ）参照 次いで、上記１層目のＳｉＣ薄膜片２Ａの表出する裏面
におけるパッド用拡散領域４が形成されていない領域即
ち集積回路が形成されている素子領域に対応する領域上
に、例えば前記同様の接着剤９Ｂを介して２段目になる
半導体チップｌ０ＩＢを、ＳｉＣ薄膜−片２Ｂ側を対向
させて接着し、次いで前記同様の手段により２段目チッ
プ１０１ＢのＳｉ基板１８部を選択的にエンチング除去
する。Refer to FIG. 2(b) Next, on the exposed back surface of the first layer SiC thin film piece 2A, an area where the pad diffusion area 4 is not formed, that is, an area corresponding to the element area where the integrated circuit is formed. For example, the second-stage semiconductor chip 10IB is bonded with the SiC thin film piece 2B side facing each other via the same adhesive 9B as described above, and then the Si substrate 18 of the second-stage chip 101B is bonded by the same means as described above. selectively etching away parts.

第２図（Ｃ）参照 次いで、上記２層目のＳｉＣ薄膜片２Ｂの表出する裏面
における素子領域に対応する領域上に、前記同様の接着
剤９Ｃを介して３段目になる半導体チップｌ０ＩＣを、
ＳｉＣ薄膜片２Ｃ側を対向させて接着し、次いで前記同
様の手段により３段目チップ１０１ＣのＳｉ基板ＩＣ部
を選択的にエツチング除去する。Refer to FIG. 2(C) Next, a semiconductor chip 10IC, which will be the third layer, is placed on the region corresponding to the element region on the exposed back surface of the second-layer SiC thin film piece 2B via the same adhesive 9C as described above. of,
The SiC thin film pieces 2C are bonded together with their sides facing each other, and then the Si substrate IC portion of the third-stage chip 101C is selectively etched away using the same means as described above.

なお、ＳｉＣ薄膜片の重ね合わせは３第に限られるもの
ではなく、上記手法を繰り返し必要なだけ重ねることが
可能である。Note that the stacking of the SiC thin film pieces is not limited to the third method, and it is possible to stack the SiC thin film pieces as many times as necessary by repeating the above method.

第２図（ｄ）参照 次いで、上記ＳｉＣ薄膜片２Ａ、２Ｂ、２Ｃが積層され
ている基板８上にＣＶＤ法によりＰＳＧからなる厚さ０
．５μｍ程度の絶縁膜１０を形成し、通常のりソグラフ
ィ手段により該絶縁膜１０に各ＳｉＣ薄膜片加、２Ｂ、
２Ｃにおけるパッド用拡散領域４の底面を表出する開口
を形成し、次いで通常の配線形成手段により上記絶縁膜
１０上にその開口部を通じて各層のＳｉＣ薄膜片２Ａ、
２Ｂ、２Ｃのパッド用拡散領域４間を相互に接続するＡ
Ｉ等の第２の金属膜配線１１を形成し、本発明に係る３
次元構造の大規模集積回路が完成する。Refer to FIG. 2(d) Next, a film made of PSG with a thickness of 0 is deposited on the substrate 8 on which the SiC thin film pieces 2A, 2B, and 2C are laminated by the CVD method.
．． An insulating film 10 with a thickness of about 5 μm was formed, and each SiC thin film piece was added to the insulating film 10 by ordinary lamination lithography.
An opening exposing the bottom surface of the pad diffusion region 4 in 2C is formed, and then SiC thin film pieces 2A of each layer are formed on the insulating film 10 through the opening by ordinary wiring forming means.
A which interconnects the pad diffusion regions 4 of 2B and 2C.
A second metal film wiring 11 such as I is formed, and the third metal film wiring according to the present invention is
A large-scale integrated circuit with a dimensional structure is completed.

第３図は該実施例の上記第２の金属膜配線１１の形成が
完了した状態をわかりやすく示した模式斜視図で、図中
の各符号は第２図と同一対象物を示している。FIG. 3 is a schematic perspective view clearly showing the state in which the formation of the second metal film wiring 11 of this embodiment is completed, and each reference numeral in the figure indicates the same object as in FIG. 2.

なお、第２図、第３図において、ＳｉＣ薄膜片から絶縁
性基板の図示されない配線パターンに導出される金属膜
配線は省略されている。Note that in FIGS. 2 and 3, metal film wiring led out from the SiC thin film piece to a wiring pattern (not shown) on the insulating substrate is omitted.

第５図は他の実施例、即ち上記実施例と同様の積層手段
を用いて形成され、且つ前記実施例と異なる積層構造の
３次元構造大規模集積回路を模式的に示した図で、（ａ
）は透視平面図、（ｂ）はＡ−Ａ矢視断面図である。FIG. 5 is a diagram schematically showing another embodiment, that is, a three-dimensional structured large-scale integrated circuit formed using the same stacking means as in the above embodiment, and having a stacked structure different from the above embodiment. a
) is a perspective plan view, and (b) is a sectional view taken along the line A-A.

図中、２Ａ＋　、２Ａｚ　、２Ａ３．２Ａ４は１層目（
下層）のＳｉＣ薄膜片、２Ｂは２層目（上層）のＳｉＣ
薄■り片、４はパッド用拡散領域、７は被覆絶縁膜、８
は絶縁性基板、債、９Ｂは接着剤、１０は絶縁膜、１１
Ａは１層目のＳｉＣ薄膜片におけるパッド用拡散領域４
　（ａ図には図示されず）の底面を介して１層目のＳｉ
Ｃ薄膜片に形成されている集積回路（図示せず）同士を
相互に接続する金属膜配線、１１Ｂはパッド用拡散領域
４の底面を介して２層目の　ＳｉＣ薄膜片２Ｂに形成さ
れている集積回路（図示せず）と１層目のＳｉＣ′ａ膜
片に形成されている集積回路（図示せず）とを相互に接
続する金属膜配線を表している。In the figure, 2A+, 2Az, 2A3.2A4 are the first layer (
2B is the SiC thin film piece of the second layer (upper layer)
Thin strip, 4 is a diffusion region for pad, 7 is a covering insulating film, 8
is an insulating substrate, bond, 9B is an adhesive, 10 is an insulating film, 11
A is the pad diffusion region 4 in the first layer SiC thin film piece.
(not shown in figure a) through the bottom surface of the first layer of Si.
Metal film wiring 11B interconnecting integrated circuits (not shown) formed on the C thin film pieces is formed on the second layer SiC thin film piece 2B via the bottom surface of the pad diffusion region 4. It represents a metal film interconnection that interconnects an integrated circuit (not shown) and an integrated circuit (not shown) formed on the first-layer SiC'a film piece.

この構造においては、図（ａ）に示されるように、絶縁
性基板８上に並べて固着された複数枚の１層目のＳｉＣ
薄膜片例えば４枚のｓｔｃ　薄膜片２Ａ、、２Ａ２．２
Ａ３．２Ａ４上に跨る形で２層目のＳｉＣ薄膜片２Ｂが
固着される。従ってこの場合、下層のＳｉＣ薄膜片例え
ば４枚のＳｉＣ薄膜片２八ｒ　、２Ａｚ　、２Ａ３．２
Ａ４等は、上層のＳｉＣ薄膜片２Ｂが固着される領域に
パッド用拡散領域を設けないように予め設計されなけれ
ばならない。In this structure, as shown in FIG.
Thin film pieces, for example 4 stc thin film pieces 2A, 2A2.2
A3.2 A second layer of SiC thin film piece 2B is fixed so as to straddle A4. Therefore, in this case, the lower layer SiC thin film pieces, for example, four SiC thin film pieces 28r, 2Az, 2A3.2
A4 etc. must be designed in advance so that the pad diffusion region is not provided in the region where the upper SiC thin film piece 2B is fixed.

なお第５図において、ＳｉＣ薄膜片から絶縁性基板の図
示されない配線パターンに導出される配線は省略されて
いる。Note that in FIG. 5, wiring led from the SiC thin film piece to a wiring pattern (not shown) on the insulating substrate is omitted.

また各々のｓｉｃ　ＦＪ膜片に形成される集積回路も省
略されている。Also, the integrated circuit formed on each SIC FJ film piece is also omitted.

以上の実施例において、集積回路が形成され積層される
ＳｉＣ薄膜片の厚さは２０００人程度０あるので、それ
に対応する絶縁性基板の上面と１層目のｓｉｃ　Ｆｉ！
膜片の上面間、１層目のＳｉＣ薄膜片の上面と２層目の
ＳｉＣ薄膜片の上面間、２層目のＳｉＣ薄膜片の上面と
３層目のｓｉｃ　ＷＪ膜片の上面間等の段差は、金属膜
配線、絶縁膜、接着剤等を含めても高々１μｍ程度であ
る。従って　上記層間を接続する配線を金属薄膜によっ
て形成してもカハレージ不良による断線を生ずることが
ない。In the above embodiment, the thickness of the SiC thin film pieces on which the integrated circuit is formed and stacked is about 2000, so the corresponding upper surface of the insulating substrate and the first layer SIC Fi!
between the top surfaces of the film pieces, between the top surface of the first layer SiC thin film piece and the top surface of the second layer SiC thin film piece, between the top surface of the second layer SiC thin film piece and the top surface of the third layer SIC WJ film piece, etc. The level difference is approximately 1 μm at most, including the metal film wiring, insulating film, adhesive, and the like. Therefore, even if the wiring connecting the layers is formed of a metal thin film, disconnection due to poor coverage will not occur.

〔発明の効果〕〔Effect of the invention〕

以上説明のように本発明によれば、チップを積み重ねて
構成する３次元構造の大規模集積回路における層間の配
線接続を、ポンディングワイヤによらずに金属膜配線に
より信頼度よく形成することができる。As described above, according to the present invention, wiring connections between layers in a large-scale integrated circuit with a three-dimensional structure constructed by stacking chips can be formed with high reliability using metal film wiring instead of using bonding wires. can.

従ってワイヤ接続において生じていた変形による相互間
の接触障害等の発生がないので層間接続配線の配設密度
が向上できて高集積化が可能になり、且つボンディング
個所が減少して歩留り、信頼性の向上、及び製造コスト
の低減が図れる。Therefore, there is no occurrence of mutual contact failure due to deformation that occurs in wire connections, so the arrangement density of interlayer connection wiring can be improved, making it possible to achieve high integration.In addition, the number of bonding points is reduced, improving yield and reliability. It is possible to improve the performance and reduce the manufacturing cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜（ｂ）、（Ｃ）　−１、（Ｃ）　−２は
本発明の原理を示す工程断面図、 第２図（ａ）〜（ｄ）は本発明の方法の一実施例の工程
断面図、 第３図は同じ（一実施例の模式斜視図、第４図（ａ）〜
（ｄ）は本発明に係るチップ形成方法の工程断面図、 第５図は本発明の他の実施例の模式図で（ａ）は透視平
面図、（ｂ）はＡ−Ａ矢視断面図、第６図は従来構造の
模式断面図 である。 図において、 ｌはＳｉ基板、 ２はＳｉＣ薄膜、 ２Ａ、　２Ｂ、　２ＣはＳｉＣ薄膜片、３は素子領域、 ４はパッド用拡散領域、 ５は層間絶縁膜、 ６は第１の金属（導電）膜配線 （チップ内配線）、 ７は被覆絶縁膜、 ８は絶縁性基板、 ９Ａ、　９Ｂ、　９Ｃは接着剤、 １０は絶縁膜、 １１は第２の金属（導電）膜配線 （チップ外配線）、 １０１は半導体チップ を示す。 シトづ芒り月／ｌ源チ里２７￥　Ｔ工オヱ町面りつ第　
ｊ　図 木受ＦＪｐｔの方３去の一莞杷例ｎニオ監ぼ汀面図第　
２Ｉ！］ 第 図 （ａ） 透 視千面 図 （ト） Ａ−Ａ　　久ネｔｍｔｉ　　図 ／Ｓ、発明６ワイ也ｄフ実方セＬ４り１σフ横ｙ（回部 図 ／＄イ色日月にイ子、う乎ップカ４〃綻方５すＪ）目乙
臘ｍｔｉ回部 図 従来構造の樺戎朝面図 第 図Figures 1 (a) to (b), (C) -1, and (C) -2 are process sectional views showing the principle of the present invention, and Figures 2 (a) to (d) are one example of the method of the present invention. The process cross-sectional view of the example and FIG. 3 are the same (the schematic perspective view of one example and FIG. 4(a) to
(d) is a process cross-sectional view of the chip forming method according to the present invention, FIG. 5 is a schematic diagram of another embodiment of the present invention, (a) is a perspective plan view, and (b) is a cross-sectional view taken along the line A-A. , FIG. 6 is a schematic cross-sectional view of the conventional structure. In the figure, l is a Si substrate, 2 is a SiC thin film, 2A, 2B, 2C are SiC thin film pieces, 3 is an element region, 4 is a diffusion region for a pad, 5 is an interlayer insulating film, 6 is a first metal (conductive) Membrane wiring (wiring inside the chip), 7 is a covering insulating film, 8 is an insulating substrate, 9A, 9B, 9C are adhesives, 10 is an insulating film, 11 is a second metal (conductive) film wiring (outside chip wiring) , 101 indicates a semiconductor chip. Shitozu Amonritsuki/l Genchiri 27 yen T Koe Town Men Ritsudai
j Map of FJPT
2I! ] Figure (a) Perspective thousand-sided view (G) Child, Uobupuka 4〃Return 5suJ) Meottomti rotation diagram Traditional structure of Kabaeki morning view Diagram

Claims (1)

【特許請求の範囲】 第１の半導体基板と、該半導体基板上にエピタキシャル
成長させた該第１の半導体とエッチングの選択性を有す
る第２の半導体薄膜と、該第２の半導体薄膜の表面部に
能動素子が形成されてなる素子領域と、該第２の半導体
薄膜に選択的に該第２の半導体薄膜の表面から裏面に達
する深さに形成されたパッド用拡散領域と、該第２の半
導体薄膜上に形成された第１の絶縁膜と、該第１の絶縁
膜上に形成され該能動素子とパッド用拡散領域上の所定
位置に対応する第１の開口を有する第１の絶縁膜と、該
第１の絶縁膜上に形成され該第１の開口を通じて該能動
素子間及び該能動素子と該パッド用拡散領域間を接続し
て集積回路を構成する第１の導電膜配線とを有し、該集
積回路の選別試験を完了してなる同種若しくは異種の複
数の半導体チップを用い、 下段になる該半導体チップを、該第１の半導体に対して
エッチングの選択性を有する絶縁性基板上に、該第２の
半導体薄膜側を対向させて、直に若しくは該第１の半導
体とエッチングの選択性を有する絶縁物質を介し接着す
る工程と、 エッチング手段により該下段の半導体チップの第１の半
導体基板を選択的に除去して、該絶縁性基板上に該下段
の半導体チップの第２の半導体薄膜片を裏面を表出した
状態で固着残留せしめる工程と、 該下段の第２の半導体薄膜片裏面の該パッド用拡散領域
が配設されていない領域上に、該下段と同種若しくは異
種の上段になる該半導体チップを、該第２の半導体薄膜
側を対向させて、該第１の半導体とエッチングの選択性
を有する絶縁物質を介し接着する工程と、 エッチング手段により該上段の半導体チップの半導体基
板を選択的に除去して、該下段の第２の半導体薄膜裏面
の該パッド用拡散領域が配設されていない領域の上部に
、上段の第２の半導体薄膜片を裏面を表出した状態で固
着残留せしめる工程と、 該第２の半導体薄膜片が重着された第２の半導体薄膜片
積層体及び該絶縁性基板上に第２の絶縁膜を形成する工
程と、 該第２の絶縁膜に、該下段及び上段の第２の半導体薄膜
片におけるパッド用拡散領域の裏面を個々に表出する複
数の第２の開口を形成する工程と、 該複数の第２の開口を通じ、該上段の第２の半導体薄膜
のパッド用拡散領域と該下段の第２の半導体薄膜のパッ
ド用拡散領域とを相互に接続する第２の導電膜配線を形
成する工程とを有することを特徴とする大規模集積回路
の製造方法。[Scope of Claims] A first semiconductor substrate, a second semiconductor thin film having etching selectivity with respect to the first semiconductor epitaxially grown on the semiconductor substrate, and a surface portion of the second semiconductor thin film. an element region in which an active element is formed; a pad diffusion region selectively formed in the second semiconductor thin film to a depth reaching from the front surface to the back surface of the second semiconductor thin film; and the second semiconductor thin film. a first insulating film formed on a thin film; a first insulating film formed on the first insulating film and having a first opening corresponding to a predetermined position above the active element and the pad diffusion region; , a first conductive film wiring formed on the first insulating film and connecting between the active elements and between the active element and the pad diffusion region through the first opening to configure an integrated circuit. Then, using a plurality of semiconductor chips of the same type or different types that have been subjected to a screening test for the integrated circuit, the lower semiconductor chip is placed on an insulating substrate that has etching selectivity with respect to the first semiconductor. a step of adhering the second semiconductor thin film directly or through an insulating material having etching selectivity with the second semiconductor thin film side facing each other; and by etching the first semiconductor chip of the lower semiconductor chip. selectively removing the semiconductor substrate and leaving a second semiconductor thin film piece of the lower semiconductor chip fixedly remaining on the insulating substrate with its back surface exposed; On the region on one back surface where the pad diffusion region is not provided, place the semiconductor chip that will become the upper layer of the same type or different type from the lower layer with the second semiconductor thin film side facing the first semiconductor chip. and a step of bonding the pad through an insulating material having etching selectivity, and selectively removing the semiconductor substrate of the upper semiconductor chip by etching means, and forming a diffusion region for the pad on the back surface of the lower second semiconductor thin film. a step of fixing and remaining an upper second semiconductor thin film piece with its back side exposed on the upper part of the area where the second semiconductor thin film piece is not disposed; and a second semiconductor thin film on which the second semiconductor thin film piece is heavily attached. a step of forming a second insulating film on the stack of pieces and the insulating substrate, and individually applying the back surfaces of the pad diffusion regions of the lower and upper second semiconductor thin film pieces to the second insulating film; forming a plurality of exposed second openings, and diffusing a pad diffusion region of the upper second semiconductor thin film and a pad diffusion region of the lower second semiconductor thin film through the plurality of second openings; A method for manufacturing a large-scale integrated circuit, comprising the step of forming a second conductive film wiring interconnecting the regions.
JP63289211A 1988-11-16 1988-11-16 Manufacturing method of large-scale integrated circuit Expired - Lifetime JP2734025B2 (en)

Priority Applications (1)

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JP63289211A JP2734025B2 (en) 1988-11-16 1988-11-16 Manufacturing method of large-scale integrated circuit

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JP63289211A JP2734025B2 (en) 1988-11-16 1988-11-16 Manufacturing method of large-scale integrated circuit

Publications (2)

Publication Number Publication Date
JPH02134860A true JPH02134860A (en) 1990-05-23
JP2734025B2 JP2734025B2 (en) 1998-03-30

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486541B2 (en) 1993-08-04 2002-11-26 Hitachi, Ltd. Semiconductor device and fabrication method
EP1455394A1 (en) * 2001-07-24 2004-09-08 Seiko Epson Corporation Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486541B2 (en) 1993-08-04 2002-11-26 Hitachi, Ltd. Semiconductor device and fabrication method
EP1455394A1 (en) * 2001-07-24 2004-09-08 Seiko Epson Corporation Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipment
EP1455394A4 (en) * 2001-07-24 2007-02-14 Seiko Epson Corp Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipment

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