JPH02132941A - Circuit switching system - Google Patents

Abstract

PURPOSE:To stabilize synchronizing characteristic, and to improve a bit error rate even if the sudden change of a CLK signal due to the circuit switching of a high-order section occurs by providing a switching detection circuit and a transmitted code processing board and a frame synchronizing board, etc. CONSTITUTION:A switching detection output 51 outputted from the switching detection circuit 5 in the receiving-end circuit switching device 106 of the high-order section is inserted into an auxiliary signal bit 61 through the transmitted code processing board 6 of a sending-end circuit switching device 201, and is inputted to the frame synchronizing board 7 of the receiving-end circuit switching device 206. The auxiliary signal bit is detected by the board 7, and is prolonged by definite time by a noise band width control circuit 8, and a noise band width control signal 81 to control the noise band width of the bit synchronizing PLL circuit 9 of a demodulator 205 is outputted. Then, the signal 81 controls the noise band width of the circuit 9 so as to expand it at the point of time of the realization or the cancellation of the circuit switching condition of the higher rank section, and returns it after definite time. Then, even if the sudden change of the CLK signal due to the circuit switching of the high-order section occurs, the synchronizing characteristic can be stabilized, and simultaneously, the good bit error rate can be obtained.

Description

Detailed Description of the Invention [Icheon Field of Industry] The present invention relates to a line switching system used when at least two sections of line vJ {+ section are connected in series in wireless microwave digital communication. [Prior Art] Conventionally, in a wireless microwave digital communication system in which at least two line switching sections are connected in series, each section is not controlled mutually, and each section independently performs circuit switching. I was doing it. [Challenges to be solved] However, as mentioned above, each section has a circuit disconnection.
In particular, if you do +, the section in second place is the line JPf.
When doing this, a sudden phase change occurs in the CLK signal,
There was a drawback that the PLL circuit used for bit synchronization of the demodulator became out of synchronization after the section where four-wire switching was performed. In contrast, by widening the noise band of the PLL circuit, it is possible to maintain good synchronization characteristics, but on the other hand, a problem arises in which the bit error rate of the demodulator deteriorates. The present invention was made in view of these problems, and it is possible to obtain stable synchronization characteristics even if there is a sudden change in the CLK signal due to line switching in the upper section, and also to obtain a good bit error rate. The purpose is to provide a circuit switching system that can [1000 Steps to Solve the Problem] To achieve the above object {1), the present invention provides a line switching system in which at least two line switching sections in wireless microwave digital communication are connected in series, in which line switching is performed based on line fault information and line switching status. The LJJ {+ detection circuit detects the cutting operation for troubleshooting and sends switching information for the 5th section to the line ν no moss device for the F section, and the lower section transmission is performed by the output of this cutting detection circuit. An additional bit insertion circuit inserts an auxiliary signal bit at the end, and an L
The additional bit extraction circuit outputs the auxiliary signal bit, and the output of this additional bit extraction circuit controls the noise bandwidth of the PLL circuit for bit synchronization of the repeater, and the upper section is switched immediately before the circuit vJ is executed. The configuration includes a 2l tone bandwidth control circuit that widens the noise bandwidth of the bit synchronization PLL circuit for a certain period of time after completion. [Examples] Examples of the present invention will be described below with reference to the drawings.
Ill1. FIG. 1 is a control block diagram related to the hill bandwidth control in the 17iI line switching device of this embodiment, and FIGS. 2(a) and (b)
) is a noise bandwidth control time chart of the device, and (a) shows the case of channel alarm activation/cancellation.
Figure (b) shows the case of system alarm activation/cancellation. In FIG. 1, reference numeral 106 indicates the upper section receiving end circuit cutting equipment, and the frame synchronous board 1. Recycler 3Ji # device 2. Reception code processing board 3. It has a receiving end system switching base 4 and a switching detection circuit 5. The frame infrastructure 1 monitors the transmission quality of the line, and if the transmission quality deteriorates beyond a specified value, it activates a channel alarm 11 as line failure information, which is a condition for synchronized switching of the line. The reception code processing board 3 monitors the transmission quality of the line, and when the transmission quality deteriorates below a specified value or when a failure occurs in the equipment, it activates a system alarm 3l as line failure information and sends a system alarm 3l to the system 9J8. It is a condition. The synchronous switch 2 also outputs a switching state signal 21. -H position section reception end! /] {Naffltoa's receiving end system switch 4 outputs a cut moss status signal 41. The cutting detection circuit 5 has the channel alarm l1 and the cutting moss 7m21 or the system alarm 31! /J# state 4l causes
The switching detection output 5l shown in the noise bandwidth control time chart in Figure 2 is output. Further, 201 is an F-section sending end line νJ waiting device, which has a code processor J'Jjfi6 as an additional bit insertion circuit. 206 is a receiving end circuit cutting device, which includes a frame synchronization board 7 as an additional bit extraction circuit and noise:1? It has a bandwidth control circuit 8. 205 is F section receiving end I3! The νJ. The FF detection output 5l is inserted into the auxiliary signal bin} 61 in the transmission code processing board 6 of the lower section sending end circuit switching device 201, and is converted into an auxiliary signal bit by the frame synchronization board 7 of the lower section receiving end circuit J8 device 206. is detected and the upper section line 9 line information output 7l is output. The upper section line vJ section information output 71 is the miscellaneous band of the lower section receiving end line re-J switching device 206
The lower section receiving end converter 7A 20
A noise bandwidth control signal 8l for controlling the noise bandwidth of the beat-to-beat synchronized PLL circuit 9 of No. 5 is obtained. As shown in the noise width control time chart of FIG. 2, the noise bandwidth control signal 8l performs control to widen the noise bandwidth of the PLL circuit 9 at time T1 when the line switching condition for the upper section is satisfied. At time T3, when the synchronization of the PLL circuit 9 has stabilized from the time T2 when the line re-J change is completed, the 3I sound 11? The bandwidth control is canceled and the noise bandwidth of the PLL circuit 9 is returned to its original value. Next, at time T4 when the line switching condition for the upper section is canceled.
Then, control is performed to widen the noise bandwidth of the PLL circuit, and from time T5 when the circuit switchback is completed, the PLL circuit is
At time T6, when the synchronization of the L circuit 9 has stabilized, the noise band is returned to its original value. FIG. 3 is a block diagram showing an example of a line switching section to which the system of the embodiment described above is applied. In the drawing, 101
, 111.201211 respectively indicate the sending end circuit switching device t, 102, 112, 202, 2121f modulator, 1
03, 113, 203, 213 are transmitters, 104, 11
4,204,214 is the receiver, 105,115,205
, 215 is a demultiplexer, 106, 116, 206, 216
indicates the receiving end line connection. [Effects of the Invention] As explained above, the present invention is capable of widening the noise bandwidth of the PLL circuit used for bit synchronization of the demodulator in response to sudden phase changes in the CLK signal due to line disconnection in the upper section. Therefore, stable synchronization characteristics can be obtained by {iJ, and the line!
/J# Returning the noise bandwidth to the original value after a certain period of time has the effect of obtaining a good bit error rate.

[Brief explanation of the drawing]

FIG. 1 is a control block diagram regarding noise bandwidth control in a line switching system according to an embodiment of the present invention, and FIG. 2 is (a). (b) is a noise bandwidth control time chart of the same system, and FIG. 3 is a configuration diagram showing an example of a line switching section that connects the system of the present invention to river A. 1: Frame synchronization fi 11: Channel alarm 2
Two-synchronous switching device 21 Two-synchronous switching device switching state output 3: Reception code processing board 3l: System alarm 4: Receiving end system switching device 4l: Receiving end system switching device switching state output 5: +J
J switching detection circuit 51: Switching detection circuit output 6: Transmission code processing x 61 + auxiliary signal bit 7: Frame synchronization board
71: Line switching information output 8; Noise bandwidth control circuit 81: 3l sound bandwidth control signal 9: Demodulator Tl: Channel alarm activation time or system alarm activation time and noise? fF bandwidth control time T2 two synchronization standby!
ill change time or receiving end system switch Kirin time T3: 3t sound bandwidth control release time T4: channel alarm release time or system alarm release time and noise bandwidth control time T5. Synchronous switching device ν return time or receiving end system switching device resetting time T6: Noise bandwidth control release time 101, ill, 201, 211 - Sending end line switching device 102, 112, 202, 212: Modulator 103 ,11
3,203,213: Transmitter 104,114,204,
214 + receiver 105, 115, 205, 215: demodulator 106, 116, 206, 216: receiving end line switching device

Claims (1)

[Claims] In a line switching system in which at least two line switching sections in wireless microwave digital communication are connected in tandem, a switching operation for relieving a line fault is detected based on line fault information and a line switching state, and a switching operation for line switching equipment in a lower section is detected. a switching detection circuit that sends switching information of the upper section;
An additional bit insertion circuit that inserts an auxiliary signal bit at the lower section sending end based on the output of this switching detection circuit, an additional bit extraction circuit that extracts the auxiliary signal bit at the lower section receiving end, and the output of this additional bit extraction circuit. Noise bandwidth control that controls the noise bandwidth of the PLL circuit for bit synchronization of the demodulator by controlling the noise bandwidth of the PLL circuit for bit synchronization of the demodulator, and widens the noise bandwidth of the PLL circuit for bit synchronization from immediately before the upper section performs circuit switching to for a certain period of time after the switching is completed. A circuit switching system characterized by comprising a circuit.