JPH0213105A - Power supply for fet amplifier - Google Patents
Power supply for fet amplifierInfo
- Publication number
- JPH0213105A JPH0213105A JP63163611A JP16361188A JPH0213105A JP H0213105 A JPH0213105 A JP H0213105A JP 63163611 A JP63163611 A JP 63163611A JP 16361188 A JP16361188 A JP 16361188A JP H0213105 A JPH0213105 A JP H0213105A
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- voltage
- power supply
- drain
- power
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- 239000003990 capacitor Substances 0.000 claims abstract description 26
- 230000005669 field effect Effects 0.000 claims description 7
- 230000001934 delay Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 12
- 230000003321 amplification Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 241000282376 Panthera tigris Species 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔概要〕
マイクロ波増幅器等の増幅素子として電界効果トラ、ン
ジスタＦＥＴを用いたＦＥＴ増幅器用の正のドレイン電
圧と負のゲートを投入順序を定めてデカップリングを通
してＦＥＴに供給する電源の構成に関し、
電源投入時のドレイン電流ＩＤとデカップリングコンデ
ンサの充電電流■。の和の電源電流■。[Detailed Description of the Invention] [Summary] A positive drain voltage and a negative gate for an FET amplifier using a field effect transistor or transistor FET as an amplification element of a microwave amplifier or the like are determined and the order is determined and the order is determined and the FET is connected to the FET through decoupling. Regarding the configuration of the power supply, drain current ID and decoupling capacitor charging current ■ at power-on. The power supply current of the sum of■.
が電源の最大定格出力電流より小さいＦＥＴ増幅器用の
電源を目的とし、
ソースを接地した電界効果トランジスタＦＥＴのゲート
に負のゲート電圧を加え、直列抵抗と接地間コンデンサ
からなるデカップリングを通してドレインに正のドレイ
ン電圧を加えＦＥＴにドレイン電流Ｉ、を流しデカップ
リングのコンデンサ乙こ充電電流ＩＣを流すＦＥＴ増幅
器用電源において、正電源の出力の正電圧の立上りをデ
カップリングのコンデンサが充電され定常状態に達する
まで遅らす立上り制御回路と、負電源の出力の負電圧を
一定時間だけＦＥＴのゲート電圧の所定の動作電圧より
低くトレイン電流が流れないピンチオフ電圧付近の負電
圧に下げる立下り制御回路を設け、電源投入時のＦＥＴ
のドレイン電流■。を減らしデカップリングのコンデン
サの充電電流■。Intended for power supplies for FET amplifiers whose output current is smaller than the maximum rated output current of the power supply, a negative gate voltage is applied to the gate of a field effect transistor FET whose source is grounded, and a positive voltage is applied to the drain through decoupling consisting of a series resistor and a capacitor between ground. In a power supply for an FET amplifier, which applies a drain voltage of , and flows a drain current I to the FET and a charging current IC to the decoupling capacitor, the decoupling capacitor is charged at the rise of the positive voltage of the output of the positive power supply and reaches a steady state. A rise control circuit that delays the output of the negative power supply until the current is reached, and a fall control circuit that reduces the negative voltage of the output of the negative power supply for a certain period of time to a negative voltage near the pinch-off voltage that is lower than the predetermined operating voltage of the gate voltage of the FET and at which no train current flows. FET at power on
The drain current of■. ■ Reduce the decoupling capacitor charging current.
と合わせた電源電流Ｉ、が定格最大出力電流より大とな
らぬように構成する。The configuration is such that the combined power supply current I does not exceed the rated maximum output current.
本発明はマイクロ波増幅器等の増幅素子として電界効果
トランジスタＦＥＴを用いたＦＥＴ増幅器用の電源に係
り、特にＦ Ｅ ＴのソースＳを接地し、ゲー１−Ｇに
負電圧を印加した後にドレインＤに正電圧を印加するＦ
ＥＴ増幅器用の電源の構成に関する。The present invention relates to a power supply for an FET amplifier using a field effect transistor FET as an amplification element such as a microwave amplifier, and in particular, the source S of the FET is grounded, and after applying a negative voltage to the gate 1-G, the drain D Applying a positive voltage to F
This invention relates to the configuration of a power supply for an ET amplifier.
従来のＦＥＴ増幅器用電源は、第４図のブロック図に示
す如く、増幅素子としての電界効果トランジスタＦＥＴ
ｌ０のソースＳを接地し、ゲートＧに負電圧−Ｖｏｕ
ｔを加えドレインＤに正電圧＋Ｖｏｕ ｔを加えるドレ
イン電圧用正電２ｇｔａとデーｌ−電圧用負電源２Ａか
らなる固定バイアスのＦＥＴ増幅署：）用電源であって
、該電源を動作させる場合の電源投入の順序は、第５図
の説明図のＡに示す々ｒｌ＜、ＦＥ′Ｔ’ＩＯのドレイ
ン電流Ｉ、が飽和電流１ｔ＋ｓｓに近い大電流が流れて
ＦＥＴｌ０が破壊されるのを防ぐ為、最初負のゲート電
圧Ｖ ＣＳを加え、次に正のドレイン電圧Ｖ ０５を加
えるようにしているので、同図のＢのように、飽和電流
■、３．より小さいドレイン電流ＩＤが流れる。また電
源には一般にノイズをカットするデカップリング３のコ
ンデンサＣが接地間にあるので該コンデンサＣへの充電
電流ＩＣ（同図Ｃ）も加わり結局、投入時には同図のＤ
のようにドレイン電流■。とコンデンサＣへの充電電流
Ｉ。の和として大きな電源電流Ｉ、が流れる。A conventional FET amplifier power supply uses a field effect transistor FET as an amplifying element, as shown in the block diagram of FIG.
The source S of l0 is grounded, and the gate G is applied with a negative voltage -Vou.
A fixed bias FET amplification station consisting of a positive voltage 2gta for the drain voltage and a negative power source 2A for the data l-voltage which applies a positive voltage +Vout to the drain D by adding t and applying a positive voltage +Vout t to the drain D, and when operating the power supply. The order in which the power is turned on is as shown in A in the explanatory diagram of FIG. , first a negative gate voltage V CS is applied, and then a positive drain voltage V 05 is applied, so as shown in B in the same figure, the saturation currents ■, 3. A smaller drain current ID flows. In addition, since the power supply generally has a decoupling capacitor C (3) between the ground and the ground, a charging current IC (C in the same figure) is also added to the capacitor C.
Drain current as ■. and charging current I to capacitor C. A large power supply current I flows as the sum of .
すると電源電流■、が電源に定めノ、−最大重（δ出力
電流Ｉ。、４ＡＸを越えたり、図示しない４源の過電流
保護回路が動作してＦＥＴｌ０に「−・＞７ ｙ；バイ
アス電圧が加わらないことがある。そｒ・□゛）為、電
源の最大定格出力電流ｉ。ＨＡＸをＦＥＴｌ０の定常動
作時の電流■、。より十分に大きい値にし５なければな
らないのでＦＥＴ増幅器用電源がコスト・アンプとなる
という問題がｊチイ、。Then, if the power supply current ■, exceeds the maximum load (δ output current I., 4AX) determined by the power supply, the 4-source overcurrent protection circuit (not shown) operates, and the bias voltage Therefore, the maximum rated output current of the power supply i. The problem is that it becomes a cost amplifier.
本発明は電源投入時の電源電流１ｓを低く抑えて、電源
の最大定格出力電流ｌ。□８と定常動作時の電源電流１
．。との差が小さいＦＥＴ増幅器用の電源を提供するこ
とを課題とする。The present invention suppresses the power supply current 1 s at power-on to a low value, thereby increasing the maximum rated output current 1 of the power supply. □8 and power supply current 1 during steady operation
．． . An object of the present invention is to provide a power supply for an FET amplifier with a small difference between the two.
この課題は、デカップリング回路３のコンデンサＣの充
電電流１ｃは、ＦＥＴｌ０のドレイン電圧ｖ ｎｓの大
小によって決まるが、ドレイン電流ＩＤは、ゲーＩ・電
圧ＶＣＳによって変化することに着目し、第１図に示す
如く、正電源１の出力の正電圧＋νｏｕｔの立上りをデ
カップリング３のコンデンサＣが充電され定常状態に達
するまで遅らす立上り制御回路１１と、負電源２の出力
の負電圧−Ｖｏｕ ｔを一定時間だけＦＥＴのゲート電
圧ＶＣＳの通常の動作電圧Ｖ ＧＯより低くドレイン電
流■、が流れないピンチオフ電圧付近の負電圧Ｖｐに下
げる立下り制御回路２１を設け、電源投入時に先ず、正
のドレイン電圧用型＃１の出力電圧Ｖ ＯＳがデカップ
リング３のコンデンサＣを充電し定常状態に達するまで
の間、負のゲート電圧用電源２の出力電圧Ｖ Ｇ３を通
常の動作電圧Ｖ Ｇｏより下げる事によって電源投入時
のＦＥＴｌ０のドレイン電流■。を凍らし電源電流Ｉ、
が電源の定格最大出力電流■。ＭＡＸより大とならぬよ
うにする、即ち、負のゲート電圧Ｖ ＣＳをＦＥＴのド
レイン電流Ｉ、が流れないピンチオフ電圧付近の負の大
きい電圧ｖ２に設定し次に正のドレイン電圧Ｖ ＤＳを
零から徐々に上昇するように構成する本発明によって解
決する。This problem was solved by focusing on the fact that the charging current 1c of the capacitor C of the decoupling circuit 3 is determined by the magnitude of the drain voltage Vns of the FET 10, but the drain current ID changes depending on the gate I and the voltage VCS. As shown in , there is a rise control circuit 11 that delays the rise of the positive voltage +νout of the output of the positive power supply 1 until the capacitor C of the decoupling 3 is charged and reaches a steady state, and a rise control circuit 11 that delays the rise of the positive voltage +νout of the output of the positive power supply 1 and keeps the negative voltage -Vout of the output of the negative power supply 2 constant. A fall control circuit 21 is provided to lower the gate voltage VCS of the FET to a negative voltage Vp near the pinch-off voltage that is lower than the normal operating voltage VGO and the drain current does not flow. Until the output voltage VOS of type #1 charges the capacitor C of decoupling 3 and reaches a steady state, the output voltage VG3 of the negative gate voltage power supply 2 is lowered below the normal operating voltage VGo. Drain current of FET10 when turned on ■. Freezes the power supply current I,
■ The rated maximum output current of the power supply. In other words, set the negative gate voltage V CS to a large negative voltage v2 near the pinch-off voltage at which the FET drain current I does not flow, and then set the positive drain voltage V DS to zero. This problem is solved by the present invention, which is configured to gradually rise from .
本発明のＦＥＴ増幅器用電源の構成を示す第１図の原理
図において、
■は、電界効果トランジスタＦＥＴｌ０のドレインＤに
正電圧のドレイン電圧Ｖ ＤＳを供給するドレイン電圧
用正電源である。In the principle diagram of FIG. 1 showing the configuration of the FET amplifier power supply according to the present invention, 2 is a drain voltage positive power supply that supplies a positive drain voltage VDS to the drain D of the field effect transistor FET10.
ＩＯは、ソースＳを接地しゲートＧに負電圧−Ｖｏｕ
ｔを加えドレインＤに正電圧＋Ｖｏｕｔを加える固定バ
イアスの増幅器用の電界効果トランジスタＦＥＴである
。IO has its source S grounded and its gate G connected to a negative voltage -Vou.
This is a field effect transistor FET for a fixed bias amplifier that applies a positive voltage +Vout to the drain D.
１１は、正電源１の出力の正電圧＋Ｖｏｕｔの立上りを
デカップリング３のコンデンサＣが充電され定常状態に
達するまで遅らす立上り制御回路、２は、ＦＥＴ １０
のゲートＧに負電圧−Ｖｏｕ ｔのゲート電圧ＶＧＳを
供給するゲート電圧用負電源である。11 is a rise control circuit that delays the rise of the positive voltage +Vout output from the positive power supply 1 until the capacitor C of the decoupling 3 is charged and reaches a steady state; 2 is a FET 10
This is a negative power supply for gate voltage that supplies gate voltage VGS of negative voltage -Vout to gate G of .
２１は、貫電ｒＸ２の出力の負電圧−Ｖｏｕｔを一定時
間だけＰＥＴのゲート電圧Ｖ。、の通常の動作電圧Ｖ
Ｇ。21 is the gate voltage V of PET for a certain period of time while the negative voltage -Vout of the output of the current through rX2 is applied. , the normal operating voltage V
G.
より低くドレイン電流■。が流れないピンチオフ電圧付
近の負電圧Ｖｐに下げる立下り制御回路である。■Lower drain current. This is a fall control circuit that lowers the voltage Vp to a negative voltage near the pinch-off voltage at which no voltage flows.
立上り制御回路１１は、電源投入時のドレイン電圧用電
源１の正の出力電圧Ｖ ＯＳがデカップリング３のコン
デンサＣを充電し定常状態に達するまで立上りを遅らせ
、立下り制御回路２１が、一定時間だけＦＥＴ負のゲー
ト電圧ＶＧＳをピンチオフ電圧付近の負の大きい電圧Ｖ
、に設定するのでドレイン電流１．が流れず定常電流よ
り小さい充電電流ＩＣのみが流れる。そのあと負のゲー
ト電圧ＶＧＳを前記設定電圧Ｖｐより浅くして、正のド
レイン電圧Ｖ ＤＳが正規電圧Ｖ Ｄｏへ上昇しても、
ドレイン電流Ｉ、はその定常値ｒｏｏになるだけであり
、そのドレイン電流ｒ０と充電電流■。の和の電源電流
■、は、電源投入時の全期間に亘って定常時の電流を基
にした電源の定格最大出力電流■。ＭＡＸより大きくな
る事はなくなり問題は解決される。The rise control circuit 11 delays the rise until the positive output voltage VOS of the drain voltage power supply 1 charges the capacitor C of the decoupling 3 and reaches a steady state when the power is turned on. Only the negative gate voltage VGS of the FET is pinched off when the large negative voltage V
, so the drain current is 1. does not flow, and only the charging current IC, which is smaller than the steady current, flows. After that, even if the negative gate voltage VGS is made shallower than the set voltage Vp and the positive drain voltage VDS rises to the normal voltage VDo,
The drain current I, only reaches its steady-state value roo, and its drain current r0 and charging current ■. The sum of the power supply current ■ is the rated maximum output current of the power supply based on the steady state current over the entire period when the power is turned on. It will no longer be larger than MAX, and the problem will be solved.
〔実施例〕
第２図は本発明の実施例のＦＥＴ増幅器用電源の構成を
示す回路図であり、第３図はその動作を説明するための
特性図である。[Embodiment] FIG. 2 is a circuit diagram showing the configuration of a power supply for an FET amplifier according to an embodiment of the present invention, and FIG. 3 is a characteristic diagram for explaining its operation.
第２図において、立上り制御回路１１は、トランジスタ
Ｔｒ１．Ｔｒ２、抵抗Ｒ１，Ｒ２，Ｒ３、コンデンサＣ
１で構成され、立下り制御回路２１は、トランジスタＴ
ｒ３、抵抗Ｒ６，Ｒ７，Ｒ８，Ｒ９、コンデンサＣ２で
構成される。In FIG. 2, the rise control circuit 11 includes transistors Tr1. Tr2, resistors R1, R2, R3, capacitor C
1, the fall control circuit 21 includes a transistor T
r3, resistors R6, R7, R8, R9, and capacitor C2.
電源投入時に、負犬カーＶｉｎが先ず第３図の説明図の
■の如く入力すると、立下り制御回路２１の抵抗Ｒ６と
コンデンサＣ２の接続点Ｂに大きい負の■微分波形が現
れ、トランジスタＴｒ３がＯＮとなる。When the power is turned on, when the negative dog car Vin is first inputted as shown in the explanatory diagram of FIG. becomes ON.
するとゲート電圧用負電源２の５ＥＸＳＥ入力の電圧が
下がり接地ＧＮＤのレベルに近づく。すると負電源２の
出力端−Ｖｏｕ ｔの■電圧が大きくなり、例えば、設
定値−Ｖｏｕｔが一５ｖならば、約−８ｖの電圧Ｖｏｕ
ｔ ’になり一定時間τだけ継続する。Then, the voltage at the 5EXSE input of the gate voltage negative power supply 2 decreases and approaches the level of ground GND. Then, the voltage at the output terminal -Vout of the negative power supply 2 increases. For example, if the set value -Vout is 15V, the voltage Vout of about -8V increases.
t' and continues for a certain period of time τ.
前記接続点Ｂの■電圧が抵抗Ｒ６とコンデンサＣ２によ
り一定時間でだけ経過して−０，６ｖ以下になるとトラ
ンジスタＴｒ３がＯＦＦとなり、■の如く約−８Ｖの出
力電圧−Ｖｏｕｔ ’が一５ｖの設定値−Ｖｏｕｔにな
る。When the voltage at the connection point B becomes -0.6V or less after a certain period of time due to the resistor R6 and capacitor C2, the transistor Tr3 is turned off, and the output voltage -Vout' of about -8V as shown in ■ is -5V. The set value becomes -Vout.
電源投入時には、又、正入力＋Ｖｉｎが第３図の説明図
の■の如く抵抗Ｒ１と抵抗Ｒ２の両端に加わる。When the power is turned on, the positive input +Vin is also applied to both ends of the resistor R1 and the resistor R2, as indicated by (■) in the explanatory diagram of FIG.
すると、抵抗Ｒ１と抵抗Ｒ２の中間点へ〇〇電圧は、抵
抗Ｒ２とコンデンサＣＩにより、零Ｏｖから順次上昇す
るが、約＋０．６ｖ以下の一定時間τは、Ｔｒ２がＯＦ
Ｆ している。Ｔｒ２がＯＦＦの時はＴｒｉもＯＦＦと
なり、ドレイン電圧用正電源１の出力端＋Ｖｏｕ ｔの
■電圧、は現れずＯＶである。中間点へ〇〇電圧が＋０
．６Ｖ以上になるとＴｒ２がＯ）ＪしてＴｒｉ もＯＮ
となる。Then, the 〇〇 voltage to the midpoint between the resistor R1 and the resistor R2 increases sequentially from zero Ov due to the resistor R2 and the capacitor CI, but for a certain time τ below about +0.6 V, Tr2 is OF
F I am. When Tr2 is OFF, Tri is also OFF, and the voltage of the output terminal +Vout of the positive power source 1 for drain voltage does not appear and is OV. To the intermediate point 〇〇voltage is +0
．． When the voltage exceeds 6V, Tr2 turns O)J and Tri also turns ON.
becomes.
ＴｒｉがＯＮとなるとドレイン電圧用正電２Ｉ）；ｔｌ
の出力端＋νｏｕｔに■の如く所定電圧＋Ｖｏｕ ｔが
現れる。When Tri is turned on, the drain voltage positive voltage 2I); tl
A predetermined voltage +Vout appears at the output terminal +vout as shown in (2).
そして該所定電圧＋Ｖｏｕｔがデカップリング３のコン
デンサＣｏを充電し定常状態に達した時に規定のドレイ
ン電圧Ｖ ０５がＦＥＴｌ０のドレインＤに印加される
。When the predetermined voltage +Vout charges the capacitor Co of the decoupling 3 and reaches a steady state, a predetermined drain voltage V05 is applied to the drain D of the FETl0.
以上の如く、本発明の実施例の第２図のＦＥＴ増幅器用
電源は、その立下り制御回路２１が、一定時間τだけ負
のゲート電圧Ｖ ＧＳを、ドレイン電流の流れないピン
チオフ電圧付近の負電圧−８ｖに設定するので、ＦＥＴ
ｌ０のドレイン電流Ｉ。は流れず電源からは定常電流１
ｏｏより小さいデカップリング３のコンデンサＣｏの充
電電流Ｉ、のみが流れる。そのあと、負のゲート電圧Ｖ
ＧＳを前記負電圧８ｖより浅くし設定値−５ｖに設定し
正のドレイン電圧Ｖ ０５が正規電圧Ｖ Ｄｏへ上昇し
ても、ドレイン電流■、はその定常値■、。になるだけ
で、その定常値ＩＤＯと充電電流Ｉ、の和の電源電流Ｉ
、が電源から出力されるだけである。従って本発明の実
施例のＦＥＴ増幅器用電源は、電源投入時の電源電流Ｉ
、が電源投入の全期間に亘って定常時の電源電流を上回
らず、定常特電流を基にして定める電源の定格最大出力
電流Ｉ。ＭＡＸより大きくなる事はないので問題は無い
。As described above, in the FET amplifier power supply according to the embodiment of the present invention shown in FIG. Since the voltage is set to -8v, the FET
Drain current I of l0. does not flow, steady current 1 from the power supply
Only the charging current I of the capacitor Co of decoupling 3, which is smaller than oo, flows. Then the negative gate voltage V
Even if GS is made shallower than the negative voltage 8V and set to the set value -5V, and the positive drain voltage V05 rises to the normal voltage VDo, the drain current (2) remains at its steady value (2). The power supply current I which is the sum of the steady-state value IDO and the charging current I
, is only output from the power supply. Therefore, the FET amplifier power supply according to the embodiment of the present invention has a power supply current I when the power is turned on.
, does not exceed the steady-state power supply current during the entire power-on period, and is the rated maximum output current I of the power supply determined based on the steady-state special current. There is no problem because it will never be larger than MAX.
以上説明した如く、本発明によるＦＥＴ増幅器用電源は
、その電源投入時のそのドレイン電流とデカップリング
のコンデンサの充電電流の和の電源電流が、電源投入の
全期間に亘って定常時の電源電流を上回ることがないの
で、電源の定格最大出力電流を投入時を考慮して大きな
値に定める必要がないので、電源のコストを低減できる
効果がある。As explained above, in the FET amplifier power supply according to the present invention, the power supply current, which is the sum of the drain current and the charging current of the decoupling capacitor when the power is turned on, is equal to the steady power supply current during the entire power-on period. Since it is not necessary to set the rated maximum output current of the power supply to a large value in consideration of the power-on state, there is an effect of reducing the cost of the power supply.
第１図は本発明のＦＥＴ増幅器用電源の構成を示す原理
図、
第２図は本発明の実施例のＦＥＴ増幅器用電源の構成を
示す回路図、
第３図は本発明の実施例の動作を説明するための特性図
、
第４図は従来のＦＥＴ増幅器用電源のブロック図、
第５図は従来例の動作を説明するための説明図である。
図において、
１はドレイン電圧用正電源、２はゲート電圧用負電源、
３はデカップリング回路、１０はＦＥＴ、丁
１１は立上り制御回路、２１は立柔り制御回路である。
本発明の寅施例の重力作Σ説哨す鋒め力持１１生必＄
３ 図
ネ１尺のＦＥＴ増襦Ｉ！：、用慢ヒ源のフ゛ロック図＄
４ 図Fig. 1 is a principle diagram showing the configuration of the FET amplifier power supply of the present invention, Fig. 2 is a circuit diagram showing the configuration of the FET amplifier power supply of the embodiment of the present invention, and Fig. 3 is the operation of the embodiment of the present invention. FIG. 4 is a block diagram of a conventional FET amplifier power supply, and FIG. 5 is an explanatory diagram for explaining the operation of the conventional example. In the figure, 1 is a positive power supply for drain voltage, 2 is a negative power supply for gate voltage,
3 is a decoupling circuit, 10 is an FET, 11 is a rise control circuit, and 21 is a rise control circuit. A must-have for 11 students who will be a strong force to explain the gravity work Σ of the tiger embodiment of the present invention
3 Figure: 1-shaku FET addition I! :, Block diagram of the source of negligence $
4 Figure
Claims (1)
１０）のゲート（Ｇ）に負電源（２）の出力の負電圧（
−Ｖｏｕｔ）のゲート電圧（Ｖ＿Ｇ＿Ｓ）を加え、配線
抵抗（Ｒ）と接地間のコンデンサ（Ｃ）からなるデカッ
プリング（３）を通してドレイン（Ｄ）に正電源（１）
の出力の正電圧（＋Ｖｏｕｔ）のドレイン電圧（Ｖ＿Ｄ
＿Ｓ）を加え該ＦＥＴ（１０）にドレイン電流（Ｉ＿Ｄ
）を流し該デカップリング（３）のコンデンサ（Ｃ）に
充電電流（Ｉ＿Ｃ）を流すＦＥＴ増幅器用電源において
、正電源（１）の出力の正電圧（＋Ｖｏｕｔ）の立上り
をデカップリング（３）のコンデンサ（Ｃ）が充電され
定常状態に達するまで遅らす立上り制御回路（１１）と
、 負電源（２）の出力の負電圧（−Ｖｏｕｔ）を一定時間
だけＦＥＴ（１０）のゲート電圧（Ｖ＿Ｇ＿Ｓ）の所定
の動作電圧（Ｖ＿Ｇ＿Ｏ）より低くドレイン電流（Ｉ＿
Ｄ＿Ｓ）が流れないピンチオフ電圧付近の負電圧（Ｖ＿
Ｐ）に下げる立下り制御回路（２１）を設け、 電源投入時に立下り制御回路（２１）により一定時間だ
け負電源（２）の出力の負電圧（−Ｖｏｕｔ）をピンチ
オフ電圧付近の負電圧（Ｖ＿Ｐ）に下げ、立上り制御回
路（１１）により正電源（１）の出力の正電圧（＋Ｖｏ
ｕｔ）の立上りを遅らせてＦＥＴ（１０）のドレイン電
流（Ｉ＿Ｄ）を減らしデカップリング（３）のコンデン
サ（Ｃ）の充電電流（Ｉ＿Ｃ）と合わせた電源電流（Ｉ
＿Ｓ）が電源の定格最大出力電流（Ｉ＿Ｏ＿Ｍ＿Ａ＿Ｘ
）より大とならぬことを特徴としたＦＥＴ増幅器用電源
。[Claims] A field effect transistor FET (with its source (S) grounded)
10) is connected to the gate (G) of the negative voltage (
-Vout) is applied to the gate voltage (V_G_S), and the positive power supply (1) is applied to the drain (D) through a decoupling (3) consisting of a wiring resistance (R) and a capacitor (C) between ground.
The drain voltage (V_D) of the positive voltage (+Vout) of the output of
_S) and drain current (I_D) is added to the FET (10).
) and a charging current (I_C) flows through the capacitor (C) of the decoupling (3). A rise control circuit (11) that delays the rise until the capacitor (C) is charged and reaches a steady state, and a negative voltage (-Vout) at the output of the negative power supply (2) is applied to the gate voltage (V_G_S) of the FET (10) for a certain period of time. The drain current (I_
Negative voltage (V_
A fall control circuit (21) is provided to reduce the negative voltage (-Vout) of the output of the negative power supply (2) for a certain period of time by the fall control circuit (21) when the power is turned on. The positive voltage (+V_P) of the output of the positive power supply (1) is lowered by the rise control circuit (11)
ut) to reduce the drain current (I_D) of the FET (10) and reduce the power supply current (I_D) combined with the charging current (I_C) of the decoupling (3) capacitor (C).
_S) is the rated maximum output current of the power supply (I_O_M_A_X
) A power supply for FET amplifiers that is characterized by not being larger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63163611A JPH0213105A (en) | 1988-06-30 | 1988-06-30 | Power supply for fet amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63163611A JPH0213105A (en) | 1988-06-30 | 1988-06-30 | Power supply for fet amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0213105A true JPH0213105A (en) | 1990-01-17 |
Family
ID=15777218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63163611A Pending JPH0213105A (en) | 1988-06-30 | 1988-06-30 | Power supply for fet amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0213105A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02141110A (en) * | 1988-11-22 | 1990-05-30 | Nec Corp | Power supply circuit for fet amplifier |
| JP2007065205A (en) * | 2005-08-30 | 2007-03-15 | Denso Corp | Display device |
| JP2010103796A (en) * | 2008-10-24 | 2010-05-06 | New Japan Radio Co Ltd | Switching method of high frequency circuit, and high frequency circuit |
| JP2011146143A (en) * | 2010-01-12 | 2011-07-28 | Panasonic Corp | Microwave processing device |
| JP2013168753A (en) * | 2012-02-15 | 2013-08-29 | Fujitsu Ltd | Amplification device and amplification method |
-
1988
- 1988-06-30 JP JP63163611A patent/JPH0213105A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02141110A (en) * | 1988-11-22 | 1990-05-30 | Nec Corp | Power supply circuit for fet amplifier |
| JP2007065205A (en) * | 2005-08-30 | 2007-03-15 | Denso Corp | Display device |
| JP4626451B2 (en) * | 2005-08-30 | 2011-02-09 | 株式会社デンソー | Display device |
| JP2010103796A (en) * | 2008-10-24 | 2010-05-06 | New Japan Radio Co Ltd | Switching method of high frequency circuit, and high frequency circuit |
| JP2011146143A (en) * | 2010-01-12 | 2011-07-28 | Panasonic Corp | Microwave processing device |
| JP2013168753A (en) * | 2012-02-15 | 2013-08-29 | Fujitsu Ltd | Amplification device and amplification method |
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