JPH02122652A - Multilayer wiring structure for semiconductor device - Google Patents

Multilayer wiring structure for semiconductor device

Info

Publication number
JPH02122652A
JPH02122652A JP27709588A JP27709588A JPH02122652A JP H02122652 A JPH02122652 A JP H02122652A JP 27709588 A JP27709588 A JP 27709588A JP 27709588 A JP27709588 A JP 27709588A JP H02122652 A JPH02122652 A JP H02122652A
Authority
JP
Japan
Prior art keywords
wiring
wiring layer
layer
contact hole
uppermost
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27709588A
Other languages
Japanese (ja)
Inventor
Noriyuki Terao
Original Assignee
Ricoh Co Ltd
Ricoh Res Inst Of Gen Electron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd, Ricoh Res Inst Of Gen Electron filed Critical Ricoh Co Ltd
Priority to JP27709588A priority Critical patent/JPH02122652A/en
Publication of JPH02122652A publication Critical patent/JPH02122652A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To achieve high integration and to shorten photolithographic process by connecting the wiring material on the uppermost layer through an identical contact hole with all other wiring layers.
CONSTITUTION: The uppermost wiring layer, i.e., a third wiring layer 6, is connected through the same (common) contact hole 9 with all other wiring layers, i.e., an Si substrate 1 and a second wiring layer 4. Preferably, the diameter of the contact hole 9 increases toward the upper layer. Since the uppermost third wiring layer 6 is formed on the contact hole 9 which is formed such that a portion of each wiring layer is exposed, each wiring layer is connected firmly, degree of integration is improved considerably and mask can be matched with sufficient margin.
COPYRIGHT: (C)1990,JPO&Japio
JP27709588A 1988-11-01 1988-11-01 Multilayer wiring structure for semiconductor device Pending JPH02122652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27709588A JPH02122652A (en) 1988-11-01 1988-11-01 Multilayer wiring structure for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27709588A JPH02122652A (en) 1988-11-01 1988-11-01 Multilayer wiring structure for semiconductor device

Publications (1)

Publication Number Publication Date
JPH02122652A true JPH02122652A (en) 1990-05-10

Family

ID=17578705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27709588A Pending JPH02122652A (en) 1988-11-01 1988-11-01 Multilayer wiring structure for semiconductor device

Country Status (1)

Country Link
JP (1) JPH02122652A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397789A (en) * 1977-02-07 1978-08-26 Nec Corp Semiconductor device
JPS62118543A (en) * 1985-11-18 1987-05-29 Nec Corp Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397789A (en) * 1977-02-07 1978-08-26 Nec Corp Semiconductor device
JPS62118543A (en) * 1985-11-18 1987-05-29 Nec Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device

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