JPH02113722A - Output circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation with a small mask occupied area by using a bipolar transistor(TR) having a small mask occupied area and a high current driving capability as an output load driver and using also a comparatively small MOS TR to guarantee an output 'L' level standard. CONSTITUTION:A circuit 101 is added and a gate width of an N-channel MOS TR M11 is selected to be 1/4 of a conventional gate width or below. An 'H' level driver is an NPN bipolar TR Q11, while an 'L' level driver is an NPN bipolar TR Q12. The N-channel MOS TR M11 acts like guaranteeing the standard of output 'L' level 0.4V. Thus, the mask occupied area is decreased, and the high speed operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and more particularly to a high-speed output circuit having a bipolar/0MO8 hybrid structure.

[Conventional technology]

Conventionally, various circuit configurations have been proposed for output circuits of integrated circuits such as semiconductor memories, particularly output circuits that require high-speed operation.

FIG. 3 shows an example of a conventional output circuit. In this conventional example, N
PN type bipolar transistor Q1. This shows an output circuit using an N-channel MOS transistor Mll as an output load driver. Note that in the output circuit of this conventional example, when the output control signal DOE is at the II L 11 level, the output terminal D is
The ATA buffer signal is output to the output terminal OUT, and the DO
When E is II H11 level, Q++++ Mu are both O
It is configured so that it becomes an FF state and the output terminal OUT becomes a high impedance state.

Generally, for integrated circuits with TTL interface, the output "I Hl" level standard is 2.4v or more.
1L” level standard is 0.4v or less, power supply voltage standard is 45
~5.5 V. For output circuits that require high-speed operation, bipolar transistors with high current drive capability are suitable as driver transistors, but since the on-voltage between base and emitter is approximately 0.8 V, II
When a bipolar transistor is used as a driver on the L II level side, the output "I Ll" level standard of 0.4■ cannot be satisfied. Therefore, as in the circuit of this conventional example, “the Hu level side is a bipolar transistor.
On the If L+'' level side, an output circuit using MO8+- transistors has been used.

[Problem to be solved by the invention]

In the conventional output circuit described above, the driver on the IIL side is a MOS transistor, so in order to achieve high current drive capability, the gate width must be made very large, and as a result, the mask This has disadvantages of increasing the area occupied by the circuit and increasing the gate capacitance to be driven by the preceding circuit, resulting in a speed delay.

An example of the transistor dimensions of a conventional output circuit is ′
While the emitter length of the "H" side driver side control driver PN type bipolar transistor is 50 μm, the gate width of the N channel type MOS transistor which is the "L" side driver is 1000 μm. Comparing the area occupied on the mask, a MOS transistor (gate width 1000 .mu.m) occupies a very large area, about 10 times that of a bipolar transistor (emitter length 50 .mu.m), even considering the element isolation region.

[Means to solve the problem]

The output circuit of the present invention has a configuration in which a first bipolar transistor is provided between the output terminal and the power supply terminal, and a second bipolar transistor and a MOS transistor are further provided in parallel between the output terminal and the ground terminal. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

A first embodiment of the invention is shown in FIG. In this example,
An output circuit in which the circuit 101 is added to the conventional output circuit described above, and the gate width of the N-channel MOS transistor M11 is set to one-fourth or less of the conventional output circuit.
As in the conventional example, the level side driver is an NPN bipolar transistor Qll, and the 'L' level side driver is an NPN bipolar transistor Q12.
This is different from conventional methods. In this embodiment, the N-channel MOS transistor Mr+ outputs “L° level fi”.
It serves to guarantee 1.4V.

As an example of the transistor size of the output circuit of this embodiment, an NPN bipolar transistor Q1. .

The emitter length of QB is 50 μm and 60 μm respectively.
It is set to 0 μm. The gate width of the N-channel MOS transistor M121M+3 that drives the NPN bipolar transistor Q+2 is 80 μm.
The gate width of the base discharge N-channel type MOS transistor M14 of Q and □ is set to 5 μm. Therefore, although the output circuit of this embodiment has an increased number of elements compared to the conventional one,
It can be seen that the area occupied by the mask is significantly reduced compared to the conventional method.

A second embodiment of the invention is shown in FIG.

=5 This embodiment is a case where the data signal in the first embodiment described above is replaced with complementary signals DATA, DATA, and the sense amplifier system is a symmetrical circuit like a semiconductor memory that requires high-speed operation. Suitable if

〔Effect of the invention〕

As explained above, the present invention uses a bipolar transistor having a small mask area and high current driving ability as an output load driver, and furthermore, the output It L I
By also using a relatively small MOS transistor to ensure the + level standard, it is possible to realize an output circuit capable of high-speed operation with a small overall mask occupation area.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an output circuit of a first embodiment of the present invention, Fig. 2 is a circuit diagram showing an output circuit of a second embodiment of the invention, and Fig. 3 is a circuit diagram showing an output circuit of a second embodiment of the present invention. FIG. 2 is a circuit diagram showing a conventional output circuit. 101... Output "I L l" level side driver circuit Q, Q, 2... NPN type bipolar transistor, M 1+ + M 12+ M 131
M+4...N-channel type MOS transistor. Agent Patent Attorney Susumu Uchihara

Claims (2)

[Claims] (1) An output circuit characterized in that a first bipolar transistor is provided between an output terminal and a power supply terminal, and a second bipolar transistor and a MOS transistor are further provided in parallel between the output terminal and a ground terminal. (2) The transistor size is set so that the internal equivalent resistance of the second bipolar transistor in a conductive state is one quarter or less of the internal equivalent resistance of the MOS transistor in a conductive state. An output circuit according to claim (1).