JPH02108300A - Non-volatile storage - Google Patents

Non-volatile storage

Info

Publication number
JPH02108300A
JPH02108300A JP63261048A JP26104888A JPH02108300A JP H02108300 A JPH02108300 A JP H02108300A JP 63261048 A JP63261048 A JP 63261048A JP 26104888 A JP26104888 A JP 26104888A JP H02108300 A JPH02108300 A JP H02108300A
Authority
JP
Japan
Prior art keywords
writing
non
disturb test
dcr
q6
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63261048A
Inventor
Akira Nara
Takeshi Wada
Original Assignee
Hitachi Ltd
Hitachi Tobu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tobu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP63261048A priority Critical patent/JPH02108300A/en
Publication of JPH02108300A publication Critical patent/JPH02108300A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To attain the collective disturb test of a data line by supplying the writing voltage through a high voltage for writing and a dummy FET to all data lines of EPROM formed by a double gate non-volatile element.
CONSTITUTION: At the time of a disturb test mode, all word lines W1 and W2 become the non-selecting condition for double gate non-volatile elements Q1 to Q3 and Q4 to Q6 of 1 memory array M-ARY of EPROM by X, Y address buffer decoders XADB.DCR and YADB.DCR with respective signals DWT and DDT from a control circuit CONT, transistors Q7 to Q9 of a column switch are turned on, all word lines D1 to Dn are selected, and the high voltage for writing through a common data line CD connected to an output circuit DOB is supplied. On the other hand, all FET D16 to D18 are turned on by an output DY of the circuit CONT, the writing voltage is supplied through a dummy cell 20 to all data lines D1 to Dn, and the disturb test of all word line is collectively executed to elements Q1 to Q6 in a short time without the puncn-through.
COPYRIGHT: (C)1990,JPO&Japio
JP63261048A 1988-10-17 1988-10-17 Non-volatile storage Pending JPH02108300A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63261048A JPH02108300A (en) 1988-10-17 1988-10-17 Non-volatile storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63261048A JPH02108300A (en) 1988-10-17 1988-10-17 Non-volatile storage

Publications (1)

Publication Number Publication Date
JPH02108300A true JPH02108300A (en) 1990-04-20

Family

ID=17356338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63261048A Pending JPH02108300A (en) 1988-10-17 1988-10-17 Non-volatile storage

Country Status (1)

Country Link
JP (1) JPH02108300A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504744B2 (en) 2000-06-09 2003-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with memory test circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271100A (en) * 1985-09-24 1987-04-01 Hitachi Ltd Semiconductor integrated circuit device
JPS62229599A (en) * 1986-03-31 1987-10-08 Toshiba Corp Nonvolatile semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271100A (en) * 1985-09-24 1987-04-01 Hitachi Ltd Semiconductor integrated circuit device
JPS62229599A (en) * 1986-03-31 1987-10-08 Toshiba Corp Nonvolatile semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504744B2 (en) 2000-06-09 2003-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with memory test circuit

Similar Documents

Publication Publication Date Title
JP3948141B2 (en) The semiconductor memory device and control method thereof
US5381374A (en) Memory cell data output circuit having improved access time
EP0563082B1 (en) Hidden refresh of a dynamic random access memory
US6205071B1 (en) Semiconductor memory device including sense amplifier circuit differing in drivability between data write mode and data read mode
US6201724B1 (en) Semiconductor memory having improved register array access speed
KR100501749B1 (en) Pipeline fast access floating gate memory architecture and method of operation,
US5796660A (en) Memory device and serial-parallel data transform circuit
US5761146A (en) Data in/out channel control circuit of semiconductor memory device having multi-bank structure
US4365319A (en) Semiconductor memory device
US4608666A (en) Semiconductor memory
US6711051B1 (en) Static RAM architecture with bit line partitioning
EP0293798B1 (en) Non-volatile memory ciruit using ferroelectric capacitor storage element
US4649522A (en) Fast column access memory
US5862099A (en) Non-volatile programmable memory having a buffering capability and method of operation thereof
JP2812099B2 (en) Semiconductor memory
EP0030245B1 (en) Semiconductor memory device
KR100433713B1 (en) A semiconductor memory device
US5936881A (en) Semiconductor memory device
US4675850A (en) Semiconductor memory device
EP0196586A2 (en) Static semiconductor memory device
US6088270A (en) Sense amplifier with local write drivers
US5999441A (en) Random access memory having bit selectable mask for memory writes
US4538245A (en) Enabling circuit for redundant word lines in a semiconductor memory array
KR960001778B1 (en) Dual port memory and the data transferring method
US5155705A (en) Semiconductor memory device having flash write function