JPH0210619B2 - - Google Patents

Info

Publication number
JPH0210619B2
JPH0210619B2 JP59091208A JP9120884A JPH0210619B2 JP H0210619 B2 JPH0210619 B2 JP H0210619B2 JP 59091208 A JP59091208 A JP 59091208A JP 9120884 A JP9120884 A JP 9120884A JP H0210619 B2 JPH0210619 B2 JP H0210619B2
Authority
JP
Japan
Prior art keywords
bit
nb1c
output
circuit
frequency divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59091208A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60235549A (ja
Inventor
Koji Nishizaki
Hiroyasu Sumya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59091208A priority Critical patent/JPS60235549A/ja
Publication of JPS60235549A publication Critical patent/JPS60235549A/ja
Publication of JPH0210619B2 publication Critical patent/JPH0210619B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/048Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59091208A 1984-05-08 1984-05-08 nB1C符号信号のCビツト同期方式 Granted JPS60235549A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59091208A JPS60235549A (ja) 1984-05-08 1984-05-08 nB1C符号信号のCビツト同期方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59091208A JPS60235549A (ja) 1984-05-08 1984-05-08 nB1C符号信号のCビツト同期方式

Publications (2)

Publication Number Publication Date
JPS60235549A JPS60235549A (ja) 1985-11-22
JPH0210619B2 true JPH0210619B2 (fr) 1990-03-08

Family

ID=14020006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59091208A Granted JPS60235549A (ja) 1984-05-08 1984-05-08 nB1C符号信号のCビツト同期方式

Country Status (1)

Country Link
JP (1) JPS60235549A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03123315U (fr) * 1990-03-28 1991-12-16

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62151045A (ja) * 1985-12-25 1987-07-06 Nec Corp 多重変換装置の同期信号伝送方式
JPS633533A (ja) * 1986-06-23 1988-01-08 Nec Corp ワ−ド同期回路
FR2631762B1 (fr) * 1988-05-18 1991-02-15 Cit Alcatel Dispositif de synchronisation de trame pour un train numerique synchrone partage en blocs au moyen d'un code par blocs et structure en trames

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03123315U (fr) * 1990-03-28 1991-12-16

Also Published As

Publication number Publication date
JPS60235549A (ja) 1985-11-22

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