JPH02101737A - Compound semiconductor wafer - Google Patents
Compound semiconductor waferInfo
- Publication number
- JPH02101737A JPH02101737A JP25427488A JP25427488A JPH02101737A JP H02101737 A JPH02101737 A JP H02101737A JP 25427488 A JP25427488 A JP 25427488A JP 25427488 A JP25427488 A JP 25427488A JP H02101737 A JPH02101737 A JP H02101737A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- gaas substrate
- thickness
- xalxas
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 23
- 239000013078 crystal Substances 0.000 claims abstract description 16
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 5
- 239000007791 liquid phase Substances 0.000 claims abstract description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000000654 additive Substances 0.000 claims 1
- 238000005336 cracking Methods 0.000 abstract description 5
- 238000005452 bending Methods 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 229910052733 gallium Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000007790 solid phase Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 29
- 238000005498 polishing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野J
本発明はAfJAS混晶比が高く膜厚の厚いGaAlA
sエピタキシャル層をGaAs基板上に成長させた化合
物半導体ウェハ若しくは該ウェハのGaAs基板を全て
除去したGaAj Asから成る化合物半導体fウェハ
に関する。Detailed Description of the Invention [Industrial Field of Application J] The present invention is directed to GaAlA having a high AfJAS mixed crystal ratio and a thick film thickness.
The present invention relates to a compound semiconductor wafer in which an s epitaxial layer is grown on a GaAs substrate, or a compound semiconductor wafer made of GaAjAs from which the GaAs substrate of the wafer is completely removed.
[従来の技術]
従来から、GaAs基板上にGa1−xAlxASをエ
ピタキシャル成長させたウェハは、電界効果トランジス
タ(FEET)発光ダイオード(しED)等に広く使用
されている。[Prior Art] Conventionally, wafers in which Ga1-xAlxAS is epitaxially grown on a GaAs substrate have been widely used for field effect transistors (FEETs), light emitting diodes (EDs), and the like.
LEDにおいて、GaAsl5板上のG” 1−XΔf
1xAsllは発光出力を向上させる目的で光透過層と
して機能するが、発光波長が7000A以FのnJ視L
EDにおいては、AjAs混晶比Xが0.4以上、厚さ
が100μm以上のGa1−xAll、XAs8が要求
される。好ましくは、光を吸収してしまうGaAs基板
を除去して、Ga1−xAρxAs[を基板として使用
することが望ましい。In LED, G"1-XΔf on GaAsl5 plate
1xAsll functions as a light transmission layer for the purpose of improving the light emission output, but the nJ viewing L with a light emission wavelength of 7000A or less
In ED, Ga1-xAll and XAs8 are required to have an AjAs mixed crystal ratio X of 0.4 or more and a thickness of 100 μm or more. Preferably, the GaAs substrate that absorbs light is removed and Ga1-xAρxAs[ is used as the substrate.
尚、このGa1−xAfJxAS層の導電型はLEDの
構造により選択されるが、Ga1−xAfJxAs層に
通電する構造の場合は、Zn或いは−1−e等をドープ
してn型或いはP型の層とし、通電しない構造の場合に
はノンドープの低キヤリア濃度の層とすることか−・般
的である。The conductivity type of this Ga1-xAfJxAS layer is selected depending on the structure of the LED, but in the case of a structure in which current is passed through the Ga1-xAfJxAs layer, an n-type or p-type layer is doped with Zn or -1-e. In the case of a structure in which no current is applied, a non-doped layer with a low carrier concentration is generally used.
[発明が解決しようとする課題]
ところで、GaAsとAJIAsの格子定数は約900
℃で一致するが、熱膨張係数αが夫々−〇−1
α =6.8X10 ℃ 、α =5.2Ga
As AfJAs×10 ℃
と異なる。Ga1−xAfJxASの熱膨張係数はα
とα
GaAs All Asとの間の値をとり、△fJ
As混晶比Xによって決定される。従って、AfJAS
混晶比Xが高い程熱膨張係数はα/J Asに近づき、
又低い稈αGaAsに近づく。実際にQaASW板上に
約900℃でGa1−xAN xAsを液相エピタキシ
ャル成長させた場合には、成長温度ではAρAS混晶比
Xの大小にかかわらず両者の格子定数がほぼ一致するも
のの、室温まで冷却して取出すと、第2図に示すように
、GaAs基板2とG a 1−x A fJ x A
s BJ 3との熱膨張係数の差によりつTハ1はG
a 1−x A ’J x A S HA 3側に凸
状に湾曲してしまう。我々の実験ではこのウェハの湾曲
はノンドープ、Znドープ及びTeドープの各ウェハに
おいても殆ど差はないことが確認された。又、湾曲の大
きさはウェハの面積が太きく、又Ga1−xAfJxA
S層3のAIIAS混晶比Xが高いほど顕著であり、ウ
ェハ直径が40mmでAlAs混晶比Xが0.4以上、
1つ層の厚さが1100u以上の場合には、湾曲が30
0μm以上に達してウェハに亀裂が生じ、素f形成が極
めて困難になるという問題があった。[Problem to be solved by the invention] By the way, the lattice constant of GaAs and AJIAs is about 900.
℃, but the thermal expansion coefficient α is -〇-1 α = 6.8X10 ℃, α = 5.2Ga
AsAfJAs×10℃
different from. The thermal expansion coefficient of Ga1-xAfJxAS is α
and α GaAs All As, and △fJ
It is determined by the As mixed crystal ratio X. Therefore, AfJAS
The higher the mixed crystal ratio X, the closer the thermal expansion coefficient is to α/JAs,
It also approaches low culm αGaAs. In fact, when Ga1-xANxAs is liquid-phase epitaxially grown on a QaASW plate at about 900°C, the lattice constants of the two are almost the same regardless of the size of the AρAS mixed crystal ratio X at the growth temperature, but when cooled to room temperature. When taken out, as shown in FIG. 2, the GaAs substrate 2 and Ga 1-x A fJ
Due to the difference in thermal expansion coefficient with s BJ 3, T
a 1-x A'J x A SHA It curves convexly toward the 3 side. Our experiments have confirmed that there is almost no difference in the curvature of this wafer among non-doped, Zn-doped, and Te-doped wafers. In addition, the size of the curvature is determined by the large area of the wafer and Ga1-xAfJxA.
The higher the AIIAS mixed crystal ratio X of the S layer 3, the more remarkable it is.
If the thickness of one layer is 1100u or more, the curvature is 30
There is a problem in that when the thickness reaches 0 μm or more, cracks occur in the wafer, making it extremely difficult to form the element f.
そのため、これまでもAjAs混晶比混晶高XGa1−
xAgxAS層をエピタキシャル成長させた大面積のウ
ェハを量産することができず、その解決策が強く望まれ
ていた。又、GaAs基板を除去してGa1As基板を
製造してしま1−x x
うとしても、つ1ハが大きく湾曲しているため平坦なG
a1−xAfJxAS基板を得ることはできず、GaA
s基板を研磨除去し場合にはウェハが割れてしまうとい
う問題があった。Therefore, until now AjAs mixed crystal ratio mixed crystal high XGa1-
It is not possible to mass produce large area wafers on which xAgxAS layers are epitaxially grown, and a solution to this problem has been strongly desired. Also, even if you try to remove the GaAs substrate and manufacture a Ga1As substrate, it will not be possible to produce a flat G1 because the glass is greatly curved.
It is not possible to obtain a1-xAfJxAS substrate, and GaA
There is a problem in that when the s-substrate is removed by polishing, the wafer breaks.
本発明の目的は、上記した従来技術の問題点に鑑み、A
IIAS混晶比Xが0.4以上で旦つ厚さが100μm
以上のGa1.、xAll xAsエビタギシャル層を
GaAs基板上に成長させても、ウェハの湾曲が小さく
亀裂が生ずることのない大面積で且つ量産性に優れた化
合物半導体エピタキシャルウェハを提供することにある
。In view of the problems of the prior art described above, an object of the present invention is to
IIAS mixed crystal ratio X is 0.4 or more and thickness is 100 μm
The above Ga1. , x All
[課題を解決するための手段]
本発明の要旨は、GaAs基板上に液相エピタキシャル
成長させたGa1−x A’J x AS (0,4≦
X〈1、厚さ100μm以上)にゲルマニウムを3 X
1017ctx−”以上添加していることにある。[Means for Solving the Problems] The gist of the present invention is to provide Ga1-x A'J x AS (0,4≦
x (1, thickness 100 μm or more) with germanium 3 x
The reason is that more than 1017 ctx-" is added.
[実 施 例1
第1図にGa1.AρxASエピタキシャル層、のドー
パント及びキャリア濃度とウェハの湾曲の大きさの関係
を示す。ウェハは直径が40m、GaAs基板の厚さ3
50 u m 1G a 1−x A j xASエピ
タキシャル層の厚さが300μm、 Al1As混晶比
が0.4である。エピタキシャル層のドーパントがTe
1Znの場合はギヤリア濃度に依らずウェハの湾曲は3
00μm以上と大きく、多くの場合(60〜80%)
G a 1−x A j x A sエピタキシャル層
の表面には亀裂が生じている。[Example 1 Fig. 1 shows Ga1. The relationship between the dopant and carrier concentration of the Aρx AS epitaxial layer and the magnitude of wafer curvature is shown. The wafer has a diameter of 40 m and a GaAs substrate thickness of 3
The thickness of the 50 μm 1G a 1-x A j xAS epitaxial layer is 300 μm, and the Al1As mixed crystal ratio is 0.4. The dopant in the epitaxial layer is Te.
In the case of 1Zn, the curvature of the wafer is 3 regardless of the gearia concentration.
00 μm or more, in many cases (60-80%)
Cracks are generated on the surface of the G a 1-x A j x As epitaxial layer.
−・方Geドープの場合はキャリア濃度が高くなるにつ
れ、湾曲の大きさは低減し、キャリア濃度力3×101
7c!ll−3以上テハウJハノ湾曲ハ2o。- In the case of Ge doping, the magnitude of the curvature decreases as the carrier concentration increases, and the carrier concentration force is 3 × 101
7c! ll-3 or more Tehau J Hano Curved Ha2o.
μm以下となり、エピタキシャル層の表面の亀裂も見ら
れない。上記理由によりGeドープの場合のキャリア1
1度は3 X 1017ax−3以上が望ましい。It is less than μm, and no cracks are observed on the surface of the epitaxial layer. For the above reasons, carrier 1 in the case of Ge doping
1 degree is preferably 3 x 1017ax-3 or more.
尚、Ga1−x AJ xAsエビタギャル層のAρA
S混晶比Xが0.4以ドの場合及び厚さが100μm以
下の場合にも、本発明を適用することにより、当然湾曲
の大幅な低減を図る口とができる。In addition, Ga1-x AJ x As AρA of the Evita gal layer
By applying the present invention even when the S mixed crystal ratio
GaAs基板の特性、厚さ等は任意に選ぶことが可能で
あり、いずれの場合も十分な効果が1qられる。The characteristics, thickness, etc. of the GaAs substrate can be arbitrarily selected, and in any case, a sufficient effect of 1q can be obtained.
又、本発明はGa1−xAll xAs、’rビタキシ
ャル層の中のGeの濃度を3 X 1017am−3以
上にすれば良いのであって、この時、他の物質、例えば
Zn、Te、その伯の物質を同時に添加しても差し支え
なく、むしろ電気特性等の制御のために任意に選ぶこと
により、ウェハの実用性が向上する。Furthermore, in the present invention, the concentration of Ge in the Ga1-xAll There is no problem even if the substances are added at the same time, but rather, the practicality of the wafer is improved by arbitrarily selecting them to control electrical characteristics and the like.
このように、本発明によれば、湾曲の小さなウェハを得
ることができるため、ウェハが大面積であってもウェハ
表面に亀裂が生ずることなく、量産が可能である。又、
GaAs基板を研磨除去した場合には、得られたGa1
−x 11xAsllに加わる歪が小さいため、割れが
発生することなくほぼ平坦なGa1−x AN xAs
ウェハを高歩留りで得ることができる。As described above, according to the present invention, it is possible to obtain a wafer with small curvature, so even if the wafer has a large area, mass production is possible without cracking the wafer surface. or,
When the GaAs substrate is removed by polishing, the obtained Ga1
-x 11x As the strain applied to Asll is small, Ga1-x AN xAs is almost flat without cracking.
Wafers can be obtained with high yield.
実施例1
直径40aw、厚さ350μm1結晶面方位(100)
のGaAs基板上にGa、GaAs、A1及びGeから
なる溶液を用い、成長開始温度900℃で液相エピタキ
シャル成長法により、厚さ400um、Ge(r)濃a
3 X 1017am−3(f)Ga1−xA!Jx
As (X=0.4〜0.5)エピタキシャル層を形成
した。この時のウェハ湾曲は200μm以下であり、エ
ピタキシャル層表面及びGaAs基板等に亀裂の発生が
無かった。Example 1 Diameter 40 aw, thickness 350 μm 1 Crystal plane orientation (100)
A 400 um thick Ge(r)-concentrated a
3 X 1017am-3(f)Ga1-xA! Jx
An As (X=0.4-0.5) epitaxial layer was formed. The wafer curvature at this time was 200 μm or less, and no cracks were generated on the surface of the epitaxial layer, the GaAs substrate, etc.
次にエピタキシャル層表面を研磨して、エピタキシャル
層の厚さを250μmとし、次いでQaAS基板側基板
層してGaAs基板を全て除去し、Ga1.All x
Aslilだけからなる厚さ200μmのQa A
fJ、Asウェハを得た。研磨の過−x
程を通じて亀裂は発生せず、収率90%以上で上記のウ
ェハを製造することが出来た。Next, the surface of the epitaxial layer was polished to a thickness of 250 μm, and then the QaAS substrate side was layered, and the entire GaAs substrate was removed, and the Ga1. All x
Qa A with a thickness of 200 μm consisting only of Aslil
fJ, As wafer was obtained. No cracks were generated during the polishing process, and the above wafer could be manufactured with a yield of 90% or more.
実施例2
直径40履、厚さ350μm1結晶面方位(100>の
G a A S ki根板上Ga、GaAs。Example 2 Diameter 40 mm, thickness 350 μm 1 crystal plane orientation (100>G a AS ki root plate Ga, GaAs.
AI、Ge、及びInからなる溶液を用い成長開始温度
900℃で液相エピタキシャル成長法により、厚さ40
0μm、キャリア濃度1×10181 のP型Ga
Aj As (X=0.4〜1−× ×
0.5)エピタキシャル層を形成した。ここでGeの添
加聞は、Ga、−xAJI xAsエピタキシャル層に
おけるi度が3X1011α−3になるようにした。こ
の時ウェハの湾曲は実施例1と同様に200μm以下に
なり、亀裂も生じなかった。更に実施例1と同様に研磨
を行い、P型のGa1−xA11xAsエビタキシャル
−ウェハの高収率で得た。The film was grown to a thickness of 40°C by liquid phase epitaxial growth using a solution consisting of AI, Ge, and In at a growth starting temperature of 900°C.
P-type Ga with 0 μm and carrier concentration of 1×10181
Aj As (X=0.4 to 1−××0.5) epitaxial layer was formed. Here, Ge was added so that the i degree in the Ga, -xAJI xAs epitaxial layer was 3X1011α-3. At this time, the curvature of the wafer was 200 μm or less as in Example 1, and no cracks were generated. Further, polishing was performed in the same manner as in Example 1, and a high yield of P-type Ga1-xA11xAs epitaxial wafers was obtained.
[発明の効果]
以上に説明した如く、本発明によれば、GaAs基板上
に液相エピタキシャル成長させた0a1.AN XAs
層にGeを3X10 ax 以l添加したことによ
り、Ga1−xAlxASのΔjAs混晶比Xが0.4
以上、厚さが100μm以上であっても湾曲の小さな化
合物半導体つ1ハを得ることができる。よって、ウェハ
表面に亀裂が生ずることもなく、大面積の化合物半導体
1クエ八を高歩留りで】産することができる。。又、G
aAs基板を除去する場合、湾曲による歪が小さいため
に得られるGa A11) Asウェハが1−x
x
割れることがなく、はぼ平坦なGa1−xA1xASウ
ェハを高歩留りで得ることができる。[Effects of the Invention] As explained above, according to the present invention, Oa1. AN XAs
By adding 3x10 ax or more of Ge to the layer, the ΔjAs mixed crystal ratio X of Ga1-xAlxAS is 0.4.
As described above, a compound semiconductor chip with small curvature can be obtained even if the thickness is 100 μm or more. Therefore, a large area of compound semiconductors can be produced at a high yield without cracking the wafer surface. . Also, G
When removing the aAs substrate, the GaA11) As wafer obtained is 1-x due to the small distortion due to curvature.
x It is possible to obtain flat Ga1-xA1x AS wafers with high yield without cracking.
第1図はGa、−xA、I! xAsエピタキシャル層
のキャリア濃度とウェハの湾曲の大きさの関係を示す説
明図、第2図はGaAs基板上にAjlAS混晶比Xが
0.4以上、厚さが100μm以上のGa1−x Al
XAs1i!を液相エピタキシャル成長させた室温での
化合物半導体ウェハを示す説明図である。
1:ウェハ、
2:GaAs基板、
3 : Ga1−x 1)xAs。Figure 1 shows Ga, -xA, I! An explanatory diagram showing the relationship between the carrier concentration of the xAs epitaxial layer and the degree of curvature of the wafer.
XAs1i! FIG. 2 is an explanatory diagram showing a compound semiconductor wafer at room temperature that has been subjected to liquid phase epitaxial growth. 1: Wafer, 2: GaAs substrate, 3: Ga1-x1)xAs.
Claims (1)
AlAs混晶比Xが0.4≦X<1で且つ厚さが100
μm以上のGa_1_−_xAl_xAS層が形成され
ているウェハにおいて、前記Ga_1_−_xAl_x
AS層にゲルマニウムが3×10^1^7cm^−^3
以上添加されていることを特徴とする化合物半導体ウェ
ハ。 2、上記GaAs基板が全て除去されてなることを特徴
とする特許請求の範囲第1項記載の化合物半導体ウェハ
。[Claims] 1. AlAs mixed crystal ratio X is 0.4≦X<1 and the thickness is 100% by liquid phase epitaxial growth on a GaAs substrate.
In a wafer on which a Ga_1_-_xAl_x AS layer of μm or more is formed, the Ga_1_-_xAl_x
Germanium in the AS layer is 3 x 10^1^7cm^-^3
A compound semiconductor wafer characterized by containing the above additives. 2. The compound semiconductor wafer according to claim 1, wherein the GaAs substrate is completely removed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25427488A JPH02101737A (en) | 1988-10-08 | 1988-10-08 | Compound semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25427488A JPH02101737A (en) | 1988-10-08 | 1988-10-08 | Compound semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02101737A true JPH02101737A (en) | 1990-04-13 |
Family
ID=17262694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25427488A Pending JPH02101737A (en) | 1988-10-08 | 1988-10-08 | Compound semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02101737A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6599760B2 (en) * | 2001-02-06 | 2003-07-29 | Sumitomo Mitsubishi Silicon Corporation | Epitaxial semiconductor wafer manufacturing method |
JP2010155219A (en) * | 2008-12-27 | 2010-07-15 | Yushin Precision Equipment Co Ltd | Spin coating apparatus |
-
1988
- 1988-10-08 JP JP25427488A patent/JPH02101737A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6599760B2 (en) * | 2001-02-06 | 2003-07-29 | Sumitomo Mitsubishi Silicon Corporation | Epitaxial semiconductor wafer manufacturing method |
JP2010155219A (en) * | 2008-12-27 | 2010-07-15 | Yushin Precision Equipment Co Ltd | Spin coating apparatus |
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