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JPH0192994A - Dynamic random access memory - Google Patents

Dynamic random access memory

Info

Publication number
JPH0192994A
JPH0192994A JP25012987A JP25012987A JPH0192994A JP H0192994 A JPH0192994 A JP H0192994A JP 25012987 A JP25012987 A JP 25012987A JP 25012987 A JP25012987 A JP 25012987A JP H0192994 A JPH0192994 A JP H0192994A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
line
memory
bit
switches
sense
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25012987A
Inventor
Michihiro Inoue
Toshiro Yamada
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To obtain a high density memory system suitable for large capacity memory by arranging two bit line pairs to both sides of a sense amplifier via a selector switch so as to drive selectively only one set of bit line pairs during one operating cycle.
CONSTITUTION: With a selection signal line SS1 at '1' and a line SS2 at '0', then switches S1, S3 are turned on and switches S2, S4 are turned off and bit line pairs BL1, BL1 are connected selectively to the sense amplifier. With the line SS1 at '0' and the line SS2 at '1' conversely, the lines BL2, BL2 are connected to the sense amplifier via the switches S2, S4. Thus, either the selector switches S1, S3 or the switches S2, S4 is selected by the address signal to select either the upper or lower bit line for the operation. Then the memory cell constitution where a memory cell exists all cross points among word lines and bit lines offering advantage for high density is employed and one sense amplifier is arranged as to two bit lines thereby realizing high density of a large capacity memory.
COPYRIGHT: (C)1989,JPO&Japio
JP25012987A 1987-10-02 1987-10-02 Dynamic random access memory Pending JPH0192994A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25012987A JPH0192994A (en) 1987-10-02 1987-10-02 Dynamic random access memory

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP25012987A JPH0192994A (en) 1987-10-02 1987-10-02 Dynamic random access memory
US07157263 US4888732A (en) 1987-02-23 1988-02-18 Dynamic random access memory having open bit line architecture
KR880001845A KR920001328B1 (en) 1987-02-23 1988-02-23 Dram having open bit line structure
KR910008537A KR910008925B1 (en) 1987-10-02 1991-05-25 Dynamic type random acess memory having open bit structure

Publications (1)

Publication Number Publication Date
JPH0192994A true true JPH0192994A (en) 1989-04-12

Family

ID=17203258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25012987A Pending JPH0192994A (en) 1987-10-02 1987-10-02 Dynamic random access memory

Country Status (1)

Country Link
JP (1) JPH0192994A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0607547A1 (en) * 1993-01-19 1994-07-27 International Business Machines Corporation Two transistor one capacitor trench DRAM cell
JP2005503663A (en) * 2001-06-08 2005-02-03 マイクロン テクノロジー インコーポレイテッド Sense amplifier and architecture for open digit array

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183955A (en) * 1985-02-08 1986-08-16 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183955A (en) * 1985-02-08 1986-08-16 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0607547A1 (en) * 1993-01-19 1994-07-27 International Business Machines Corporation Two transistor one capacitor trench DRAM cell
JP2005503663A (en) * 2001-06-08 2005-02-03 マイクロン テクノロジー インコーポレイテッド Sense amplifier and architecture for open digit array

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