JPH0191518A - Clock generating device - Google Patents

Abstract

PURPOSE:To attain stable operation even when number of stages of delay elements is increased by selecting a clock of a proper phase among clocks of various phases obtained by delay at plural inverters so as to output the clock subject to phase control. CONSTITUTION:A reference pulse A, clocks T1-T3 having an edge of a prescribed phase and signals ST1-ST3 representing whether or not the clock is selected surely are outputted from a 1st clock selection circuits 1 connected in series. The clock is processed by a 2nd clock selection circuit 2 comprising inverters 6, 7, OR gates 8, 9 and an AND-OR gate 10, the clock having the edge of a prescribed phase with the reference pulse A is selected among the clocks T1-T3 and the result is outputted as the clock T subject to phase control. Even when the number of stages is increased and the delay is extended, the clock duty is kept nearly constant.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clock generation device that is effective for use in a clock generation section of a time base correction device (hereinafter referred to as TBC).
In particular, it stably generates a clock signal for time axis correction of a reproduction signal of a video tape recorder (hereinafter referred to as a VTR).

Conventional technology Digital TBC generally A/D converts the reproduced video signal using a clock synchronized with the horizontal synchronization signal and burst signal reproduced by a VTR, writes it into memory, reads it with a clock without time axis fluctuation, and then converts the reproduced video signal to D/D. By performing A conversion, a video signal from which time axis fluctuations have been removed is obtained.

The clock used for the A/D conversion of the digital TBC and the memory write control as described above is a phase-locked loop (hereinafter referred to as PLL) that is an integer multiple of the horizontal frequency from the horizontal synchronization signal reproduced from the conventional VTR. In order to correct the phase error of the PLL, a clock with a frequency of The phase of the clock created by is controlled. Methods for controlling the phase of the clock created by the PLL include those that perform phase modulation (for example, Japanese Patent Application Laid-Open No. 57-190488), and methods that reset the oscillation phase of the oscillator in the PLL (for example, Japanese Patent Application Laid-Open No. 61-56585). However, all of them require an analog circuit having a critical path and are not suitable for converting the digital TBC into a digital LSI. Therefore, by connecting a plurality of semiconductor delay elements in series, the PLL
A conceivable method is to create a plurality of clocks each having a different phase from the clock created in , and select and output the one having the same phase as the horizontal synchronizing signal or burst signal reproduced from the VTR.

Problems to be Solved by the Invention However, when the clock is delayed, the duty of the clock changes and the operation of the circuit becomes unstable.
In order to have a phase control range of 360° or more, it is necessary to ensure a delay amount of one clock period or more when passing through all stages of delay elements, so if you try to increase the precision of phase control, the number of clock delay stages will increase. , the circuit for selecting a clock of a desired phase from among the delayed clocks becomes very large. For this reason, there is a limit to the increase in the number of delay stages, and the accuracy of phase control cannot be increased. Further, it requires an expensive delay line as a delay element, and is not suitable for semiconductor implementation. In view of the above-mentioned problems, the present invention provides a clock generation device that operates stably, can be easily integrated into an LSI, and can be realized with a relatively small circuit scale in terms of phase control accuracy.

Means for Solving the Problems In order to solve the above problems, the clock generation device of the present invention includes a plurality of inverters connected in series that input continuous clocks at a substantially constant frequency and generate clocks of various phases. an extraction circuit that inputs a reference pulse serving as a reference for phase control and the clocks of the various phases, and extracts and outputs a clock whose edge phase has a fixed relationship with the reference pulse from the clocks of the various phases; A first clock selection circuit equipped with a determination circuit that determines whether or not a clock has been extracted in a circuit and outputs the result is configured such that the inverter output of the last stage of the plurality of inverters is the first stage of another first clock selection circuit. a plurality of first clock selection circuits connected so as to be input to an inverter, and an extracted clock and a judgment result are input from each of the plurality of first clock selection circuits, and the phases of the reference pulse and the edge are constant. a second selection circuit that selects and outputs a clock having a relationship of A phase-controlled clock is obtained as an output.

Effect of the Invention With the above-described configuration, the present invention can provide a clock generation device that operates stably even when the number of stages of delay elements is increased and that increases in circuit size are extremely small.

Embodiment Hereinafter, an embodiment of the clock generation device of the present invention will be described with reference to the drawings. FIG. 1 is a system diagram of a clock generation device in an embodiment of the present invention, and FIG. 2 is a specific circuit example of the first clock selection circuit 1 in FIG. 1. In FIG. 1, the clock CK before phase control is input to the first stage inverter 3, and its output CK
+ becomes the first-stage inverter input in the first clock selection circuit 1. For example, if the number of stages of inverters for delay in the first clock selection circuit 1 is four, the output CKs of the final stage is input to the inverter input of the first stage of the first clock selection circuit 1 connected next. connected to. Signal A is a reference pulse, and the clock selection circuit l of each section 1
is input. hundred. . ,.

Q, , is a signal that exchanges information about how the phase of the delayed clock changes before and after the selection circuit in the first clock selection circuit 1. Since the first clock selection circuit 1 in the last column cannot input information on a later clock phase from the next stage, a flip-flop 5 for clock phase detection is required in the final stage.

Similarly, the flip-flop 4 at the first stage is arranged before the first clock selection circuit 1 at the first stage. As described above, each of the first clock selection circuits 1 connected in series outputs a clock T I" having an edge of a constant phase with respect to the reference pulse A.
T 3 and a signal ST 3 indicating whether the clock has been definitely selected are output. In this embodiment, S T 3 is a logical value when the clock is selected. "H" is output, and if not, "L" is output.

The above clocks T1 to T3 and signals S T + to S T
3 is inverter 6.7, OR gate 8.9, AND-
A second clock selection circuit 2 consisting of an OR gate 10 selects a clock having an edge at a constant phase with one reference pulse A from among T and -T3 and outputs it as a phase-controlled clock T. There is. The second clock selection circuit 2 in the embodiment of FIG. 1 selects and outputs T1 when ST is "H", and does not select the other clocks Tz and T:l. Similarly, a certain first clock selection circuit 1 obtains a clock of a desired phase, and the first
When the signal indicating whether a clock is definitely selected in the clock selection circuit 1 of the clock selection circuit 1 becomes "H", the first
All clock outputs of the clock selection circuits are ignored.

In the above configuration, the period of the input clock GK is τ
. If the total clock delay time from CK to CK, 3 in FIG. 1 is τ, it is sufficient that τ,>τe/2.

The reason why the total delay amount τ should be 2 or more of one period of the clock is because the delay element is an inverter, so if the clock is delayed to create a phase of 08 to 180 degrees, the phase of the inverted clock will be 180 degrees. This is because the phase will be ~360''. In this case, the duty of the clock is assumed to be 50%, and in reality, τ is set larger to allow for some margin. Also, lowering the clock frequency or changing the phase If it is desired to improve the accuracy of control, this can be achieved by increasing the number of stages of the first clock selection circuit 1 connected in series.

Next, a circuit example of the first clock selection circuit in FIG. 1 will be described with reference to FIG. 2.

FIG. 3 shows a waveform diagram of each part in FIG. 2. In the circuit example shown in FIG. 2, 101 to 104 are inverters for clock delay in the first clock selection circuit 1. In the circuit example shown in FIG.

To explain the operation, the inverter 3 and flip-flop 4 at the first stage and the flip-flop 5 at the final stage are the same as those in the embodiment shown in FIG. 1. Also, in FIG. 2, the signals T, , STX are the signals T, ~T 3 , STX in FIG.
T r to ST, respectively. Clock CK and reference pulse A are the same as in FIG. In FIG. 2, the clock CK before phase control is input, and inversion and delay processing are performed in the first stage inverter 3 and inverters 101 to 104. The clocks CKn to CK, l+4, which are inverted and delayed from the clock CK, are the first-stage flip-flop 3 and the flip-flop 1 of the first clock selection circuit 1.
11 to 114 and the final stage flip-flop 5 are simultaneously latched by the reference pulse A. As shown in FIG. There is a delay of Δt between the inputs and outputs of 101 to 104, respectively. Here, when comparing the inverter output of one stage and the inverter output of the second stage, there is a time when the logical values of Hs, "L, and ' are different at the same time due to the delay. For example, as shown in Fig. 3 (al (b)
(C) (dl (el(f) (g) As shown in (h), when CK, , +1 is "H" at the rising edge of pulse A, but CK, l, etc. are "L", N
The output -S n+2 of the AND gate 133 becomes L''.

At this time, a clock having a rising edge approximately at the same time as pulse A is outputted from the inverter 123 as K yI *2. Generally Ss (m=1.2.
3. -・", n-1, n, n+1, ......) is "
In the case of "L", 1- becomes a clock with a rising edge at approximately the same time as pulse A.Theoretically, the outputs Q and Q@*1 of adjacent flip-flops become "L" or "L" at the same time. When the level becomes "H", there should be a clock whose edge is approximately at the same time as the rising edge of pulse A at the D (data) input of those adjacent flip-flops. A clock having an edge at approximately the same time as the rising edge of pulse A may be detected from the output of . The falling edge is input to the flip-flop.In this way, if the set amplifier time of the D input of the flip-flop is different between the rising and falling edges, it will cause malfunction.
In the circuit example shown in the figure, an appropriate clock is detected from the outputs of flip-flops in one stage and two stages later, and the circuit is configured so that detection can be performed only at the rising edge of the D input of the flip-flop.

Due to the above operation, the clocks appearing at the outputs of the inverters 121 to 124 are 1- to CK-9. A signal indicating whether or not to select that clock. . .

The NAND gates 131 to 134 output. With the clock created as above, I got 1 to 1. 3 and signal ¥7
By inputting .about.D□ to the 0R-AND gate 140, a phase-controlled clock is output to the output T8. Furthermore, if no clock is selected, the output T8 becomes "H". Here, flip-flop 11
1 to 114, inverters 121 to 124, and NAND gates 131 to 134.0R-AND gate 140 constitute an extraction circuit 20 for clock extraction. In the first clock selection circuit 1, if you want to increase the amount of clock delay per circuit or increase the accuracy of phase control, inverters 101 to 104, flip-flops 1
11-114, inverter 121-124, NAND
Number of gates 131 to 134 and 0R-AND gate 140
This can be handled by increasing the number of inputs. Extraction circuit 2
As a method of determining whether a clock has been extracted at 0, the logical product of the NAND gates 111 to 114 is calculated, and if the logical value is "L", it means that the clock has been extracted.However, the first clock selection circuit 1 Inverters 101 to 104, flip-flops 111 to 114, and inverters 121 to 12 are used when you want to increase the amount of clock delay per circuit or increase the precision of phase control.
4. Number of NAND gates 131 to 134 and 0R-AND
When the number of inputs to the gate 140 is increased, the number of inputs for calculating the logical product increases, and the circuit scale increases. This causes problems such as a longer time required to determine whether a clock has been extracted, resulting in a delayed response. The determination circuit 30 is composed of an AND-OR gate, and is a simple circuit that can quickly determine whether a clock has been extracted. Now, the delay time between the input of inverter 101 and the output of inverter 104 is τ0, and inverter 3
The delay time between the input of the inverter 113 and the output of the inverter 113 is τ2, and τml=τ, 2<τc/2. CK-
++, CK-z, the input of flip-flop 111 is "H" when pulse A arrives, and the input of flip-flop 5 is still "L" due to the delay. Therefore, the output Q7 of flip-flop 111 is always H', and the output Q1.4 of flip-flop 5 is always L''.

Similarly, when any of the clocks CKI, CK, -2 is extracted, the input of flip-flop 4 is "H" when the pulse arrives, and the input of flip-flop 114 is delayed. Therefore, it should still be at "L". Therefore, the output Q1 of flip-flop 4. −．
is always “H” and the output Q of the flip-flop 114
7.3 is always “L”. Based on the above, the discrimination circuit 30 is connected between the output Q7 and the inverted output of the flip-flop. 4
Based on the output Qn-+ and the inversion ratio, it is determined from 3 whether or not a clock has been extracted. The above means that even if the number of inverter stages between inverters 101 and 104 is increased by an even number, and the number of flip-flops between flip-flops 111 and 114 is increased by the same number, the above-mentioned τ1,=τ,2< This is established by satisfying the condition of τc/2. That is, it is possible to determine whether a clock has been extracted without increasing the number of determination circuits 30. Through the operation described above, the determination circuit 30 determines whether or not a clock of the desired phase has been extracted in the first clock selection circuit 1, and if it has been extracted, an "H" signal is sent to the output ST. Output. In addition, in the first clock selection circuit 1, the inverters 121 to 124 of the extraction circuit 20, the NAND
The gates 131 to 134.0R-AND gate 140 constitute a first gate circuit, and the AND-OR of the determination circuit 30
The gate is a second gate circuit, and the circuit configuration is simplified by sharing flip-flops 111 to 114 for clock phase detection.

Effects of the Invention As described above, the clock generation device of the present invention includes a plurality of serially connected inverters that input continuous clocks at a substantially constant frequency and generate clocks of various phases, and a standard that serves as a reference for phase control. an extraction circuit that inputs a pulse and clocks of the various phases, extracts and outputs a clock whose edge phase has a fixed relationship with a reference pulse from the clocks of the various phases, and determines whether the clock has been extracted by the extraction circuit; A first clock selection circuit including a determination circuit for determining and outputting the result is arranged such that an inverter output of a final stage of the plurality of inverters is input to a first stage inverter of another first clock selection circuit. The extracted clocks and judgment results are input from each of the plurality of connected first clock selection circuits and the plurality of first clock selection circuits, and a clock whose edge phase has a constant relationship with the reference pulse is selected. Since it is equipped with a second selection circuit that outputs 1. Compared to using extended lines, the total amount of delay is only about half, and stable delay is achieved.

2. If the inverter is made into an IC and configured with transistors with the same characteristics, even if the delay times for the rise and fall of the inverter output are different, the delay time for two stages will be approximately constant, and the amount of delay can be increased by increasing the number of stages. However, it is possible to maintain a substantially constant clock duty. Since 30 circuits can be divided into blocks with the same pattern, it is easy to integrate even when the circuit scale becomes large. 4. The processing time required to detect the phase of the clock, extract the clock of the desired phase, and output it can be shortened. There are other effects.

Furthermore, the determination circuit in the first clock selection circuit includes a comparison circuit that compares the phase of the clock near the first stage of the plurality of inverters with the phase of the clock near the last stage of the plurality of inverters. Even if the number of delay stages of the inverter in the first clock selection circuit is increased, the circuit scale of the determination circuit can be kept small. Further, the clock extraction circuit in the first clock selection circuit includes a plurality of flip-flops that latch the outputs of the plurality of inverters with the reference pulse, and a clock extraction circuit that extracts the phase of the reference pulse and the edge from the outputs of the plurality of flip-flops. a first gate circuit that detects a clock that has a certain relationship and passes the detected clock as an output, and the determination circuit is located near the first stage of the outputs of the plurality of flip-flops of the extraction circuit. If it is configured to include a second gate circuit that determines whether or not a clock is to be extracted from the output at the output and the output near the final stage and outputs the result, a flip-flop can be used to detect the phase of the clock. Therefore, not only can the device be constructed entirely of digital circuits, but also the flip-flop for phase detection in the extraction circuit and the determination circuit can be shared, which has the effect of simplifying the construction of the first clock selection circuit.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a clock generation device in an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of the first clock selection circuit in FIG. 1, and FIG. 2 is a waveform diagram of each part in FIG. 2. FIG. 1...First clock selection circuit, 2...
・Second clock selection circuit, 3... Inverter, 4, 5... Flip-flop, 6.7...
...Inverter, 8.9...NOR gate, 10...AND-OR gate, 20...
...Extraction circuit, 30...Determination circuit, 101-1
04...Inverter, 111-114...
...Flip flop, 121-124...
Inverter, 131-134...NAND gate, 140...0R-AND gate.

Claims (3)

[Claims] (1) A plurality of inverters connected in series generate clocks of various phases by inputting a continuous clock at a substantially constant frequency, inputting a reference pulse serving as a reference for phase control, and inputting the clocks of the various phases. It includes an extraction circuit that extracts and outputs a clock whose edge phase has a constant relationship with a reference pulse from the clocks of various phases, and a determination circuit that determines whether or not the extraction circuit extracts a clock and outputs the result. a plurality of first clock selection circuits connected such that an inverter output of a final stage of the plurality of inverters is inputted to a first stage inverter of another first clock selection circuit; , a second selection circuit inputting the extracted clock and the determination result from each of the plurality of first clock selection circuits, and selecting and outputting a clock whose edge phase has a constant relationship with the reference pulse. A clock generator characterized by: (2) The determination circuit in the first clock selection circuit is characterized by comprising a comparison circuit that compares the phase of the clock near the first stage of the plurality of inverters and the phase of the clock near the last stage of the plurality of inverters. A clock generation device according to claim (1). (3) The clock extraction circuit in the first clock selection circuit includes multiple flip-flops that latch the outputs of multiple inverters with reference pulses, and the phase of the reference pulse and edge is constant from the outputs of the multiple flip-flops. a first gate circuit that detects a clock having a relationship of The clock generator according to claim (1), further comprising a second gate circuit that determines the presence or absence of clock extraction from the output and the output near the final stage and outputs the result. Device.