JPH0191451A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0191451A
JPH0191451A JP62249626A JP24962687A JPH0191451A JP H0191451 A JPH0191451 A JP H0191451A JP 62249626 A JP62249626 A JP 62249626A JP 24962687 A JP24962687 A JP 24962687A JP H0191451 A JPH0191451 A JP H0191451A
Authority
JP
Japan
Prior art keywords
dram
memory cell
area
data storing
capacitor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62249626A
Inventor
Masamichi Ishihara
Takeshi Kizaki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62249626A priority Critical patent/JPH0191451A/en
Publication of JPH0191451A publication Critical patent/JPH0191451A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor

Abstract

PURPOSE:To increase operation speed, and decrease soft error generating rate, by constituting the memory cell of a dynamic type random access memory(DRAM) in a Stacked capacitor structure. CONSTITUTION:The memory cell M of a DRAM 21 is constituted in a stacked capacitor structure. In the memory cell M of stacked capacitor structure, the area of a diffusion layer constituting a part of a data storing capacitor element C, that is, the area of a semiconductor region 39 on the side of a memory cell selecting MISFET Qs which is not connected to a bit line 46, is reduced and the incidence provability of alpha-ray can be decreased. The area of the other parts of the data storing capacitor element C which are not affected by the alpha-ray can be enlarged to increase a data storing capacity value. Thereby realizing the high speed cycle time of the DRAM 21, and decreasing the soft error of the DRAM 21.
JP62249626A 1987-10-02 1987-10-02 Semiconductor integrated circuit device Pending JPH0191451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62249626A JPH0191451A (en) 1987-10-02 1987-10-02 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62249626A JPH0191451A (en) 1987-10-02 1987-10-02 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0191451A true JPH0191451A (en) 1989-04-11

Family

ID=17195824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62249626A Pending JPH0191451A (en) 1987-10-02 1987-10-02 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0191451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227812A (en) * 1990-02-26 1993-07-13 Canon Kabushiki Kaisha Liquid jet recording head with bump connector wiring

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227812A (en) * 1990-02-26 1993-07-13 Canon Kabushiki Kaisha Liquid jet recording head with bump connector wiring

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