JPH0151059B2 - - Google Patents
Info
- Publication number
- JPH0151059B2 JPH0151059B2 JP58093702A JP9370283A JPH0151059B2 JP H0151059 B2 JPH0151059 B2 JP H0151059B2 JP 58093702 A JP58093702 A JP 58093702A JP 9370283 A JP9370283 A JP 9370283A JP H0151059 B2 JPH0151059 B2 JP H0151059B2
- Authority
- JP
- Japan
- Prior art keywords
- base plate
- heat dissipation
- resin
- dissipation base
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 39
- 230000017525 heat dissipation Effects 0.000 claims description 23
- 239000008188 pellet Substances 0.000 claims description 20
- 239000011248 coating agent Substances 0.000 claims description 19
- 229920005989 resin Polymers 0.000 claims description 19
- 239000011347 resin Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 9
- 238000007789 sealing Methods 0.000 claims description 9
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 238000007747 plating Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000000976 ink Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 150000003839 salts Chemical class 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は樹脂封止型の半導体装置に関し、特
に中大電力用素子として好適な半導体装置に関す
るものである。
〔発明の技術的背景〕
樹脂封止型半導体装置に使用されるリードフレ
ームは、電気的伝導度、熱伝導度、耐熱性リード
フレームの加工性、リードの機械的強度等の点か
ら銅または銅合金を素材とする場合が多い。この
ような従来の銅系のリードフレームでは、キズ防
止性、耐蝕性等の点から、通常その表面にニツケ
ルメツキ、ニツケル・リン合金メツキ、銀メツキ
等の表面メツキが施される。
例えばTO−126型の装置では、略板厚が0.5mm
の銅系素材からなる薄板を用い表面メツキとして
例えばニツケルメツキを約２〜4μｍの厚みでそ
の表面全体に施し、マウント部およびボンデイン
グ部には部分的に約１〜2μｍの厚みの銀メツキ
を施す。そして、このような金属板をプレス装置
により所定の形状にプレス加工してリードフレー
ムを得る。この後、リードフレームの放熱台板上
に例えばAu−Si（金−シリコン）共晶により半導
体ペレツトをダイボンデイングし、半導体ペレツ
トの電極部とリードフレームの電極リード部とを
ワイヤボンデイングする。続いて放熱台板の半導
体ペレツトのマウントされない背面側が露出する
ような状態で例えばエポキシ樹脂等の樹脂により
上記半導体ペレツトを封止し、所定の樹脂封止部
を形成した後、リードフレームの不要な枠体或い
は連結部を切り落して製品が完成する。
〔背景技術の問題点〕
ところで、上記のように、銅系素材に２層もの
表面メツキ（上記例ではニツケルおよび銀）が実
施されたものでは、ペレツトのマウント時或いは
ワイヤボンデイング時において高温に加熱される
際に、素材との密着性が充分でない表面メツキ層
が膨らむいわゆる加熱ふくれ現象がしばしば生じ
る。このような加熱ふくれ現象のみられるリード
フレームでは、半導体ペレツトとリードフレーム
間に間隙が生じ、製品の信頼性や特性の劣化がみ
られる。例えば、このような加熱ふくれ現象を呈
したリードフレームにボンデイングワイヤを用い
てワイヤボンデイングを行つた場合、ボンデイン
グ部の接着強度が低下するため、著しい場合には
素子移動中に短絡する事故を起こす。
また、一般に表面メツキは、リードフレームに
加工されて使用される迄の保管状態、保管期間に
よりその表面が酸化し、メツキの表面が不動態化
する経時変化を生じる。このような表面が不動態
化したメツキ層を有するリードフレームに半導体
ペレツトを共晶マウントすると、金−シリコンの
共晶部に小さなボイド（巣或いは泡状空隙部）が
形成されるため、熱抵抗が増大し、ペレツトで発
生した熱が放熱台板に効果的に伝導せず、装置の
特性劣化を招く。
さらに、表面メツキ工程は、製品のコスト上昇
を招き、近年の激しい製品のコスト競争が行なわ
れている中では好ましいものではない。
〔発明の目的〕
この発明は上記のような点に鑑みなされたもの
で、製造コストの低減されかつ製品の信頼性の向
上された半導体装置を提供しようとするものであ
る。
〔発明の概要〕
すなわちこの発明に係る半導体装置では、前述
したような諸問題のある金属メツキをリードフレ
ームに施さずに、リードフレーム用金属板の放熱
台板の一方の表面上に半導体ペレツトを配設し、
リードフレームの電極リード部の所定の部位と上
記半導体ペレツトとをボンデイングワイヤ等で電
気的接続し、上記放熱台板の半導体ペレツトの配
設されない他方の表面上が露出するように樹脂封
止部を形成し、この樹脂封止部から露出する放熱
台板の裏面に樹脂からなるコーテイング膜を被着
したものである。
なお、現在ではボンデイング性やマウント性等
を劣化させることなくペレツトをメツキの施され
ていない金属リードフレームに取着する技術は確
立されているが、樹脂封止部から露出した放熱板
の耐蝕性、耐キズ性等の点からリードフレームに
はメツキを施していた。しかしながら本発明によ
るものでは放熱台板の裏面にコーテイング膜が被
着され、放熱板の耐蝕性、耐キズ性等が改善され
る。
〔発明の実施例〕
以下図面を参照してこの発明の一実施例につき
説明する。
第１図において、例えば銅系素材からなる溝板
をプレス加工し電極リード１２および素子基台と
兼用の放熱台板１３を有するリードフレーム１１
を形成し、上記放熱台板１３上に半導体ペレツト
１５を金−シリコン共晶によりマウントする。次
に半導体ペレツト１５の電極部とリードフレーム
１１の電極リード１２とをボンデイングワイヤ１
６によつてボンデイングする。
なお、ここで用いたリードフレームは、放熱台
板１３の形状が6.4×8.0mmで電極リード１２間の
間隔が1.65mmのものである。
次いで上記リードフレーム１１をエポキシ樹脂
を用いて樹脂モールドし、第２図に示すように放
熱台板１３の背面が露出した樹脂封止部１７を形
成する。なお、第２図は第１図のリードフレーム
１１を裏返した状態でみたものである。第３図
は、上記第２図の装置のＡ−A′線に沿つた断面
図であり、図の１８で示す貫通孔は、外付けの放
熱板を取り付けるための取り付け孔である。
続いて上記樹脂封止部１７から露出した放熱台
板１３の表面に付着したエポキシ樹脂中に含まれ
ているワツクスのしみ出しやゴミを例えばアセト
ン、トリクレン等で除去し、例えばゴムローラ等
を用いて放熱台板１３の露出面にコーテイング剤
を薄く延ばし、硬化させ、コーテイング膜１９を
形成する。上記コーテイング剤は、耐絶縁性、耐
溶剤性、放熱台板１３との密着性および機械的強
度の充分あるものを選定する必要があり、エポキ
シアクリレートを主成分とした紫外線硬化型イン
ク或いは熱硬化型インクなどが実用的である。本
実施例では紫外線硬化型インクとしてアサヒ化学
研究所製の商品名UVR−8000、熱硬化型インク
としてアサヒ化学研究所製の商品名PR−120を用
いた。また、インクの硬化は、紫外線硬化型イン
クの場合、ランプ出力が出力160W／cmの紫外線
装置を用い放熱台板１３との距離が約10cmとなる
ように紫外線装置を設置し、10〜20秒間紫外線を
照射して硬化させ、熱硬化型インクの場合には、
100〜120℃のオーブン中に20〜30分半導体装置を
設置し硬化させた。
またこれらのインクの塗布厚は、乾燥（硬化）
後のインクの膜厚が５〜15μｍになるようにし
た。これは、インクの膜厚が5μｍより薄い場合
には塗膜にピンホールが発生しやすく耐蝕性が十
分に得られず、加えてすりキズ等により下地の金
属面が容易に露出してしまう危険性があり、逆に
インクの膜厚が15μｍよりも厚い場合には放熱台
板１３の熱抵抗が高くなり、例えば放熱台板１３
をアルミニウムのシヤーシに取り付け実装試験を
した場合半導体素子の発熱により素子の破壊に至
る危険性を生じるためである。
〔発明の効果〕
次に本実施例における半導体装置のコーテイン
グ膜１９の強制試験結果を表１に示す。結果の欄
において〇印はコーテイング膜１９のはがれやク
ラツク等の損傷がないことを意味する。
【表】
【表】
この表に示すように上記実施例の装置における
コーテイング膜は十分な機械的強度、耐溶剤性、
放熱台板との密着性、耐熱性を有しているもので
ある。
表２はそれぞれ耐酸化性を調べた試験結果であ
る。試験項目Ａは、半導体装置を80℃、湿度90％
の雰囲気中に設置し、設置時間と放熱台板表面の
酸化の進行度を調べたもので、試験項目Ｂは半導
体装置を150℃の高温槽中に設置した場合の酸化
の進行度を調べたものである。試験は、本実施例
装置、放熱台板にメツキが施された従来装置
、放熱台板に樹脂コーテイングおよび金属メツ
キのいずれも施されていない装置の３種を対象
に行つた。なお表において〇は酸化が初期と変化
のない場合、△は酸化程度が小ないし中程度、×
は酸化が著しくみられた場合をそれぞれ示す。
【表】
この表から明らかなように放熱台板の金属面が
露出したは勿論のこと従来の金属メツキが施さ
れた装置に比べても本実施例の樹脂コーテイン
グの施された装置の方がはるかに耐酸化性が優
れているといえる。
第４図に示すものは、６個の半導体装置につい
て温度35℃の槽に入れ濃度５％の塩水を噴霧する
試験を行つた結果である。Ｃに示すものは樹脂コ
ーテイングおよび金属メツキのいずれも施されて
いない装置、Ｄは樹脂コーテイングの施された本
実施例装置それぞれにおける錆発生がみられた装
置の数を示している。なお、このグラフには示し
ていないが、従来の金属メツキの施された装置で
は試験時間48時間で６個の試料中５個程度に錆が
発生した。ここに示すように、コーテイングの施
されない装置では試験時間Ｔの増加とともに錆の
発生した不良装置の数Ｎが増加するが、樹脂コー
テイングの施された本実施例の装置では、不良装
置の発生がみられず、従来のメツキを施した装置
に比べても放熱台板の保護性、信頼性が大幅に改
善されたことが明らかになつた。
これらの試験結果から明らかなように、樹脂封
止型半導体装置から露出した金属放熱台板に樹脂
コーテイングすることにより、信頼性の高い半導
体装置を得ることができる。さらに、この半導体
装置ではリードフレームへのメツキ工程が不要
で、コーテイング膜の形成工程が非常に簡便であ
るため、大幅な製造コストの低減を図ることがで
きるものである。
尚、上記実施例ではリードフレーム材が銅系金
属からなる場合につき述べたが、これは鉄・アル
ミニウム・コバール（Fe−29、Ni−17Co）合金
や、鉄・ニツケル合金（Fe Ni−42）等の他のリ
ードフレーム材が用いられた半導体装置にも適用
可能であり、装置のパツケージの形状もTO−
126型のものに限らず、樹脂封止パツケージに放
熱台板等の金属面の露出するものであれば他の型
のものにも適用可能である。
以上のようにこの発明によれば、製造コストの
低減でき、信頼性の優れた半導体装置を提供する
ことができる。 DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and particularly to a semiconductor device suitable as a medium to high power device. [Technical Background of the Invention] Lead frames used in resin-sealed semiconductor devices are made of copper or copper in terms of electrical conductivity, thermal conductivity, workability of heat-resistant lead frames, mechanical strength of leads, etc. Often made of alloy. Such conventional copper-based lead frames are usually coated with surface plating such as nickel plating, nickel-phosphorus alloy plating, silver plating, etc. from the viewpoint of scratch prevention and corrosion resistance. For example, in the TO-126 type device, the plate thickness is approximately 0.5 mm.
Using a thin plate made of a copper-based material, the entire surface is plated with, for example, nickel plating to a thickness of about 2 to 4 μm, and the mounting portion and bonding portion are partially plated with silver to a thickness of about 1 to 2 μm. Then, such a metal plate is pressed into a predetermined shape using a press machine to obtain a lead frame. Thereafter, a semiconductor pellet is die-bonded using, for example, Au--Si (gold-silicon) eutectic on the heat dissipation base plate of the lead frame, and the electrode portion of the semiconductor pellet and the electrode lead portion of the lead frame are wire-bonded. Next, the semiconductor pellet is sealed with a resin such as epoxy resin so that the unmounted back side of the semiconductor pellet of the heat dissipation base plate is exposed, and after forming a predetermined resin sealing part, the lead frame is removed. The product is completed by cutting off the frame or connecting parts. [Problems with the Background Art] By the way, as mentioned above, when two layers of surface plating (nickel and silver in the above example) are applied to a copper-based material, it is difficult to heat the material to high temperatures during pellet mounting or wire bonding. When this is done, a so-called heating blistering phenomenon often occurs in which the surface plating layer, which does not have sufficient adhesion to the material, swells. In a lead frame that exhibits such heating blistering phenomenon, a gap is created between the semiconductor pellet and the lead frame, resulting in deterioration of product reliability and characteristics. For example, when wire bonding is performed using a bonding wire on a lead frame exhibiting such a heating blistering phenomenon, the adhesive strength of the bonding portion decreases, and in severe cases, short circuits may occur during element movement. In addition, surface plating generally undergoes changes over time such that the surface of the plating becomes oxidized and becomes passivated depending on the storage conditions and storage period until it is processed into a lead frame and used. When a semiconductor pellet is eutectically mounted on a lead frame with a plating layer with a passivated surface, small voids (cavities or bubble-like voids) are formed in the gold-silicon eutectic region, resulting in a decrease in thermal resistance. As a result, the heat generated by the pellets is not effectively conducted to the heat dissipation base plate, leading to deterioration of the characteristics of the device. Furthermore, the surface plating process increases the cost of the product, which is not desirable given the intense cost competition in products in recent years. [Object of the Invention] The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device with reduced manufacturing cost and improved product reliability. [Summary of the Invention] That is, in the semiconductor device according to the present invention, semiconductor pellets are formed on one surface of the heat dissipation base plate of the metal plate for the lead frame, without applying metal plating, which has the problems described above, to the lead frame. arranged,
A predetermined portion of the electrode lead portion of the lead frame and the semiconductor pellet are electrically connected with a bonding wire or the like, and a resin sealing portion is attached so that the other surface of the heat dissipation base plate on which the semiconductor pellet is not disposed is exposed. A coating film made of resin is applied to the back surface of the heat dissipation base plate exposed from the resin sealing portion. Currently, technology has been established to attach pellets to unplated metal lead frames without deteriorating bonding or mounting properties, but the corrosion resistance of the heat sink exposed from the resin sealing area is The lead frame was plated for scratch resistance and other reasons. However, according to the present invention, a coating film is applied to the back surface of the heat sink, and the corrosion resistance, scratch resistance, etc. of the heat sink are improved. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. In FIG. 1, a lead frame 11 is formed by pressing a grooved plate made of a copper-based material, for example, and has electrode leads 12 and a heat dissipation base plate 13 that also serves as an element base.
A semiconductor pellet 15 is mounted on the heat dissipation base plate 13 using gold-silicon eutectic. Next, the electrode portion of the semiconductor pellet 15 and the electrode lead 12 of the lead frame 11 are connected with the bonding wire 1.
Bonding is performed by step 6. Note that the lead frame used here has a heat dissipation base plate 13 in the shape of 6.4×8.0 mm and an interval between electrode leads 12 of 1.65 mm. Next, the lead frame 11 is resin-molded using epoxy resin to form a resin sealing part 17 in which the back surface of the heat dissipation base plate 13 is exposed, as shown in FIG. Incidentally, FIG. 2 shows the lead frame 11 of FIG. 1 turned over. FIG. 3 is a sectional view taken along the line A-A' of the apparatus shown in FIG. 2, and the through hole shown at 18 in the figure is a mounting hole for attaching an external heat sink. Subsequently, exuding wax and dust contained in the epoxy resin adhering to the surface of the heat dissipating base plate 13 exposed from the resin sealing part 17 are removed using, for example, acetone or trichlene, and then using, for example, a rubber roller or the like. A coating film 19 is formed by spreading a coating agent thinly on the exposed surface of the heat dissipation base plate 13 and curing it. The above-mentioned coating agent needs to be selected to have sufficient insulation resistance, solvent resistance, adhesion to the heat dissipation base plate 13, and mechanical strength. Type ink is practical. In this example, the ultraviolet curable ink used was UVR-8000 (trade name, manufactured by Asahi Chemical Research Institute), and the thermosetting ink was used, trade name PR-120 (manufactured by Asahi Chemical Research Institute). In addition, in the case of ultraviolet curable ink, the ink is cured for 10 to 20 seconds by using an ultraviolet device with a lamp output of 160 W/cm and installing the ultraviolet device so that the distance from the heat dissipation base plate 13 is approximately 10 cm. It is cured by irradiating it with ultraviolet rays, and in the case of thermosetting ink,
The semiconductor device was placed in an oven at 100 to 120°C for 20 to 30 minutes to be cured. Also, the coating thickness of these inks depends on drying (curing)
The film thickness of the subsequent ink was set to 5 to 15 μm. This is because if the ink film thickness is thinner than 5 μm, pinholes are likely to occur in the paint film, resulting in insufficient corrosion resistance, and in addition, there is a risk that the underlying metal surface may be easily exposed due to scratches, etc. On the other hand, if the ink film thickness is thicker than 15 μm, the thermal resistance of the heat sink plate 13 becomes high.
This is because if a mounting test is performed by attaching the semiconductor device to an aluminum chassis, there is a risk that the semiconductor device will generate heat and the device will be destroyed. [Effects of the Invention] Next, Table 1 shows the results of a forced test on the coating film 19 of the semiconductor device in this example. In the results column, the mark ◯ means that there is no damage such as peeling or cracking of the coating film 19. [Table] [Table] As shown in this table, the coating film in the device of the above example has sufficient mechanical strength, solvent resistance,
It has adhesion to the heat dissipation base plate and heat resistance. Table 2 shows the test results for oxidation resistance. Test item A is to test the semiconductor device at 80℃ and 90% humidity.
test item B was to examine the progress of oxidation when the semiconductor device was installed in a high-temperature bath at 150°C. It is something. The test was conducted on three types of devices: the device of this example, a conventional device whose heat dissipation base plate was plated, and a device whose heat dissipation base plate was neither resin coated nor metal plated. In the table, 〇 indicates that the oxidation is unchanged from the initial stage, △ indicates that the degree of oxidation is small to medium, and ×
1 and 2 indicate cases in which significant oxidation was observed. [Table] As is clear from this table, the metal surface of the heat dissipation base plate is exposed, and even compared to the conventional metal plating device, the resin-coated device of this example is better. It can be said that it has much better oxidation resistance. What is shown in FIG. 4 is the result of a test in which six semiconductor devices were placed in a bath at a temperature of 35° C. and were sprayed with salt water at a concentration of 5%. C shows the number of devices in which rust was observed among the devices in which neither resin coating nor metal plating was applied, and D shows the number of devices in which rust was observed in each of the devices of this example that were provided with resin coating. Although not shown in this graph, rust occurred in about 5 out of 6 samples in a conventional metal-plated device during a test period of 48 hours. As shown here, the number N of defective devices with rust increases as the test time T increases in the device without coating, but in the device of this example with resin coating, the number of defective devices does not occur. It has become clear that the protection and reliability of the heat dissipation base plate has been greatly improved compared to equipment with conventional plating. As is clear from these test results, a highly reliable semiconductor device can be obtained by coating the metal heat dissipating base plate exposed from the resin-sealed semiconductor device with a resin. Furthermore, this semiconductor device does not require a plating process for the lead frame, and the process of forming a coating film is very simple, so that manufacturing costs can be significantly reduced. In the above embodiment, the case where the lead frame material is made of copper-based metal has been described, but this may be made of iron-aluminum-kovar (Fe-29, Ni-17Co) alloy or iron-nickel alloy (Fe Ni-42). It can also be applied to semiconductor devices using other lead frame materials such as TO-
It is not limited to the 126 type, but can be applied to other types as long as the metal surface of the resin-sealed package is exposed, such as a heat dissipation base plate. As described above, according to the present invention, it is possible to reduce manufacturing costs and provide a highly reliable semiconductor device.
第１図および第２図はこの発明の一実施例に係
る半導体装置の構造を製造過程順に示す斜視図、
第３図は第２図に示す装置の断面図、第４図はこ
の発明の一実施例に係る半導体装置の塩水噴霧試
験の結果を示すグラフである。
１１……リードフレーム、１２……電極リー
ド、１３……放熱台板、１５……半導体ペレツ
ト、１６……ボンデイングワイヤ、１７……樹脂
封止部、１９……コーテイング膜。
1 and 2 are perspective views showing the structure of a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps;
FIG. 3 is a sectional view of the apparatus shown in FIG. 2, and FIG. 4 is a graph showing the results of a salt spray test on a semiconductor device according to an embodiment of the present invention. 11 ... Lead frame, 12... Electrode lead, 13... Heat dissipation base plate, 15... Semiconductor pellet, 16... Bonding wire, 17... Resin sealing part, 19... Coating film.
Claims (1)
ペレツトがマウントされた放熱台板と、上記半導
体ペレツトの所定の部位と電気的に接続された電
極リードと、上記放熱台板の他方の表面が露出す
るように上記半導体ペレツトを樹脂封止する樹脂
封止部と、上記放熱台板の他方の表面に被着され
た５〜15μｍの膜厚の樹脂製コーテイング膜とを
具備することを特徴とする半導体装置。 ２ 上記コーテイング膜の素材が紫外線硬化性樹
脂膜であることを特徴とする特許請求の範囲第１
項記載の半導体装置。 ３ 上記コーテイング膜の素材が熱硬化性樹脂膜
であることを特徴とする特許請求の範囲第１項記
載の半導体装置。[Scope of Claims] 1. A semiconductor pellet, a heat dissipation base plate on one surface of which the semiconductor pellet is mounted, an electrode lead electrically connected to a predetermined portion of the semiconductor pellet, and a heat dissipation base plate on which the semiconductor pellet is mounted. It comprises a resin sealing part for resin-sealing the semiconductor pellet so that the other surface is exposed, and a resin coating film with a thickness of 5 to 15 μm adhered to the other surface of the heat dissipation base plate. A semiconductor device characterized by: 2. Claim 1, characterized in that the material of the coating film is an ultraviolet curable resin film.
1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1, wherein the material of the coating film is a thermosetting resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58093702A JPS59218759A (en) | 1983-05-27 | 1983-05-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58093702A JPS59218759A (en) | 1983-05-27 | 1983-05-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59218759A JPS59218759A (en) | 1984-12-10 |
| JPH0151059B2 true JPH0151059B2 (en) | 1989-11-01 |
Family
ID=14089731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58093702A Granted JPS59218759A (en) | 1983-05-27 | 1983-05-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59218759A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5886400A (en) * | 1995-08-31 | 1999-03-23 | Motorola, Inc. | Semiconductor device having an insulating layer and method for making |
| JP3740117B2 (en) * | 2002-11-13 | 2006-02-01 | 三菱電機株式会社 | Power semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753947A (en) * | 1980-09-17 | 1982-03-31 | Hitachi Ltd | Transistor and electronic device containing it |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5631874Y2 (en) * | 1976-02-27 | 1981-07-29 |
-
1983
- 1983-05-27 JP JP58093702A patent/JPS59218759A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753947A (en) * | 1980-09-17 | 1982-03-31 | Hitachi Ltd | Transistor and electronic device containing it |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59218759A (en) | 1984-12-10 |
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