JPH0142126B2 - - Google Patents

Info

Publication number
JPH0142126B2
JPH0142126B2 JP12482280A JP12482280A JPH0142126B2 JP H0142126 B2 JPH0142126 B2 JP H0142126B2 JP 12482280 A JP12482280 A JP 12482280A JP 12482280 A JP12482280 A JP 12482280A JP H0142126 B2 JPH0142126 B2 JP H0142126B2
Authority
JP
Japan
Prior art keywords
layer
insulating layer
single crystal
polycrystalline silicon
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12482280A
Other languages
Japanese (ja)
Other versions
JPS5749224A (en
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12482280A priority Critical patent/JPS5749224A/en
Publication of JPS5749224A publication Critical patent/JPS5749224A/en
Publication of JPH0142126B2 publication Critical patent/JPH0142126B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に半導体装置の
基板構造を得る過程でレーザアニールにより絶縁
層上に非単結晶層を単結晶化させるようにした半
導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a non-single crystal layer on an insulating layer is made into a single crystal by laser annealing in the process of obtaining a substrate structure of the semiconductor device.

従来からイオン打ち込み等によつて生じた半導
体基板の損傷部等に高出力レーザを照射すること
で上記半導体基板の損傷部等を結晶回復させ単結
晶化することが知られている。このような結晶回
復機能はパルスレーザ照射では主に液相エピタキ
シヤル機構により説明され、CW(連続励起)レ
ーザの照射では主に固相エピタキシヤル機構によ
るものとして説明されているが高エネルギーでは
CWレーザでも液相エピが可能である。このよう
なレーザアニーリングはレーザの如き光だけにと
どまらず、粒子線等に於ても適用出来るので、本
発明ではこれらを含めてエネルギー線として説明
する。更に上記エネルギー線の照射によつて単結
晶化される多結晶シリコン層又は非晶質シリコン
層を含めて、非単結晶化層と定義する。
2. Description of the Related Art Conventionally, it has been known to irradiate a damaged portion of a semiconductor substrate caused by ion implantation or the like with a high-power laser to recover crystals of the damaged portion of the semiconductor substrate and convert it into a single crystal. Such crystal recovery function is mainly explained by a liquid phase epitaxial mechanism in pulsed laser irradiation, and is mainly explained by a solid phase epitaxial mechanism in CW (continuous excitation) laser irradiation, but at high energy
Liquid phase epitaxy is also possible with a CW laser. Such laser annealing can be applied not only to light such as a laser, but also to particle beams, etc., and therefore, in the present invention, these will be described as energy beams. Furthermore, a polycrystalline silicon layer or an amorphous silicon layer that is monocrystalized by irradiation with the energy beam is defined as a non-single crystallized layer.

第1図に示すものは、従来の半導体基板を示す
側断面図で、基板1はシリコン等よりなり、絶縁
層2を上記基板上に設ける。絶縁層としては2酸
化シリコン(SiO2)又はシリコンナイドライド
(Si3N4)でよく、該絶縁層上に非単結晶層3を
配設し、該非単結晶層上3をエネルギー線5によ
つてX方向に走査することで非単結晶化過程で非
単結晶層はエネルギー線4でメルトされ、非単結
晶層3のシリコンと絶縁層2が冷却時に固着す
る。然しこの時の非単結晶層3のシリコンの熱膨
張係数が26×10-7-1であるのに対し絶縁層の
SiO2は5×10-7-1と極めて小さいために熱膨張
係数の差によつてバイメタルの如くなり非単結晶
層3のシリコン層中に室温で大きな応力が残るた
め、良質の単結晶が得にくい。そのためこれら単
結晶上に作られた半導体装置の特性もよくない欠
点があつた。このような、非単結晶層3中の歪を
減少させるためには、SiO2膜2の厚みを薄くす
れば良いがこのようにすると基板1と単結晶化さ
れるべき非単結晶層3との静電容量が増大して半
導体素子の動作スピードが低下する欠点を生ず
る。
FIG. 1 is a side sectional view showing a conventional semiconductor substrate, in which a substrate 1 is made of silicon or the like, and an insulating layer 2 is provided on the substrate. The insulating layer may be silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), and a non-single-crystal layer 3 is provided on the insulating layer, and the top 3 of the non-single-crystal layer is exposed to an energy beam 5. Therefore, by scanning in the X direction, the non-single crystal layer is melted by the energy rays 4 in the non-single crystallization process, and the silicon of the non-single crystal layer 3 and the insulating layer 2 are fixed during cooling. However, the thermal expansion coefficient of silicon in the non-single crystal layer 3 is 26×10 -7 °C -1 , while that of the insulating layer is
Since SiO 2 is extremely small at 5×10 -7 °C -1 , it becomes like a bimetal due to the difference in thermal expansion coefficient, and large stress remains in the silicon layer of the non-single crystal layer 3 at room temperature. is difficult to obtain. As a result, semiconductor devices fabricated on these single crystals have disadvantages in that their characteristics are not good. In order to reduce such strain in the non-single-crystal layer 3, the thickness of the SiO 2 film 2 can be reduced, but in this way, the substrate 1 and the non-single-crystal layer 3 to be single-crystal are This results in a drawback that the capacitance of the semiconductor device increases and the operating speed of the semiconductor device decreases.

本発明は上述の従来の欠点に鑑みて、半導体装
置を提供するもので、絶縁層を充分に薄くし、非
単結晶層に加わる熱的応力歪を減少させ、基板1
と単結晶化されるべき非単結晶層3間の容量を小
さくすることにより高速動作可能な半導体装置を
提供することを目的とする。
In view of the above-mentioned conventional drawbacks, the present invention provides a semiconductor device in which an insulating layer is made sufficiently thin, thermal stress strain applied to a non-single crystal layer is reduced, and a substrate 1 is
It is an object of the present invention to provide a semiconductor device capable of high-speed operation by reducing the capacitance between the non-single crystal layer 3 and the non-single crystal layer 3 to be made into a single crystal.

本発明の半導体装置の特徴は、半導体基板と、
該半導体基板上に設けられた第1の絶縁層と、該
第1の絶縁層上に設けられ電気的に互いに分離さ
れた複数の領域からなるノンドープ多結晶シリコ
ン層と、該ノンドープ多結晶シリコン層上に設け
られた第2の絶縁層と、該第2の絶縁層上に設け
られエネルギー線により再結晶化されてなる単結
晶層とよりなり、前記第2の絶縁層を前記単結晶
層より十分に薄くしてなるとともに前記半導体基
板、前記第1の絶縁層、前記ノンドープ多結晶シ
リコン層、前記第2の絶縁層、前記単結晶層とに
よつて基板構造を構成し、前記単結晶層にアクテ
イブデイバイスを設けたことである。
The semiconductor device of the present invention is characterized by a semiconductor substrate;
a first insulating layer provided on the semiconductor substrate; a non-doped polycrystalline silicon layer provided on the first insulating layer and comprising a plurality of electrically isolated regions; and the non-doped polycrystalline silicon layer. a second insulating layer provided above, and a single crystal layer provided on the second insulating layer and recrystallized by energy rays; The substrate structure is made up of the semiconductor substrate, the first insulating layer, the non-doped polycrystalline silicon layer, the second insulating layer, and the single crystal layer, and the single crystal layer is made sufficiently thin. This is because an active device is installed in the system.

以下、第2図乃至第5図を参照して本発明の一
実施例を説明する。尚第1図と同一部分には同一
符号を付して示す。基板1としては10Ω・cmP型
シリコン基板を用い、その上に熱酸化膜2を1μm
成長させ、高抵抗のノンドープの多結晶シリコン
層5を上記熱酸化膜上に設け、更に該多結晶シリ
コン層上に第2の薄いSiO2層6を500Å程度酸化
させ、再びP型多結晶のシリコン層3を0.5μm厚
に設ける。このように構成した半導体装置基板の
多結晶のシリコン層3よりなる非単結晶層にエネ
ルギー線を照射して、該非単結晶層をメルト−再
固化により単結晶化される。この単結晶層にアク
テブデバイスを設けて、半導体装置が構成され
る。
Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 5. The same parts as in FIG. 1 are designated by the same reference numerals. A 10Ω/cmP type silicon substrate is used as the substrate 1, and a thermal oxide film 2 of 1 μm is deposited on it.
A non-doped polycrystalline silicon layer 5 with high resistance is formed on the thermal oxide film, and a second thin SiO 2 layer 6 of about 500 Å is oxidized on the polycrystalline silicon layer to form a P-type polycrystalline silicon layer again. A silicon layer 3 is provided with a thickness of 0.5 μm. The non-single crystal layer made of the polycrystalline silicon layer 3 of the semiconductor device substrate thus constructed is irradiated with energy rays, and the non-single crystal layer is made into a single crystal by melt-resolidification. A semiconductor device is constructed by providing an active device in this single crystal layer.

この実施例においては、第2のSiO2層6はそ
の上に形成された多結晶のシリコン層3よりも十
分に薄いため、シリコン層3では膨張率の相違に
原因する応力歪が低減される。
In this example, the second SiO 2 layer 6 is sufficiently thinner than the polycrystalline silicon layer 3 formed thereon, so that the stress strain caused by the difference in expansion coefficient is reduced in the silicon layer 3. .

上述の構成に於ける電気的な等価回路は第3図
に示すように表される。即ち第3図でコンデンサ
C1C1…は単結晶化されるべきP型多結晶のシリ
コン層3と高抵抗のノンドープの多結晶シリコン
層5間の薄いSiO2よりなる絶縁層6部分の静電
容量を、C2は高抵抗のノンドープの多結晶シリ
コン層5と基板1間のSiO2よりなる厚い絶縁層
2の静電容量を示す。多結晶シリコン層5の上、
下方向の抵抗をR1,R2、更にアクテイブデバイ
ス間の横方向の抵抗値をR3として示す。ここで
容量C1は容量C2に比べて大きな値となり、抵抗
R3もデバイス間の絶縁を大とするため高抵抗と
なされている。上記実施例ではノンドープの多結
晶シリコン層5を介して第1、第2の2層の
SiO2層2,6を設けたので、第2のSiO2層6を
薄く形成したにもかかわらず、静電容量C2,C1
の和を小とできる。したがつて、半導体装置を高
速で動作させることができる。
An electrical equivalent circuit in the above configuration is shown in FIG. In other words, in Figure 3, the capacitor
C 1 C 1 ... is the capacitance of the thin SiO 2 insulating layer 6 between the P-type polycrystalline silicon layer 3 to be made into a single crystal and the high resistance non-doped polycrystalline silicon layer 5, and C 2 represents the capacitance of the thick insulating layer 2 made of SiO 2 between the high resistance non-doped polycrystalline silicon layer 5 and the substrate 1. On the polycrystalline silicon layer 5,
The resistance in the downward direction is shown as R 1 and R 2 , and the resistance value in the lateral direction between the active devices is shown as R 3 . Here, capacitance C 1 has a larger value than capacitance C 2 , and the resistance
R3 is also made to have a high resistance in order to increase the insulation between devices. In the above embodiment, the first and second two layers are formed through the non-doped polycrystalline silicon layer 5.
Since the SiO 2 layers 2 and 6 are provided, even though the second SiO 2 layer 6 is formed thin, the capacitances C 2 and C 1
The sum of can be made small. Therefore, the semiconductor device can be operated at high speed.

第4図は本発明の他の実施例を示し、シリコン
基板1上のSiO2層7中にシリコン層5,5を分
離して、絶縁状態で配設し、上層に単結晶となる
べき非単結晶層3を配設したものである。SiO2
層は第2図と同様に第1の厚いSiO2層2と第2
の薄いSiO2層6を共有し、シリコン層5は上、
下方向に抵抗R1,R2、横方向に抵抗R4を有し、
シリコン層5,5間は完全に分離しているので、
これら素子の横方向にコンデンサC3を構成し、
第4図の等価回路は第5図の如く表すことが出来
る。勿論この場合もC1≫C2であり、シリコン層
5は第2図の如き高抵抗シリコンでなくてもよ
い。本実施例も第2図に示した実施例と同様な効
果を奏する。
FIG. 4 shows another embodiment of the present invention, in which silicon layers 5, 5 are separated and disposed in an insulating state in a SiO 2 layer 7 on a silicon substrate 1, and a non-crystalline silicon layer to be made into a single crystal is provided as an upper layer. A single crystal layer 3 is provided. SiO2
The layers are a first thick SiO2 layer 2 and a second thick SiO2 layer 2 as in Fig. 2.
sharing a thin SiO 2 layer 6, with the silicon layer 5 on top,
It has resistances R 1 and R 2 in the downward direction and resistance R 4 in the lateral direction,
Since the silicon layers 5 and 5 are completely separated,
A capacitor C 3 is configured in the lateral direction of these elements,
The equivalent circuit of FIG. 4 can be expressed as shown in FIG. Of course, in this case as well, C 1 >>C 2 and the silicon layer 5 does not have to be made of high-resistance silicon as shown in FIG. This embodiment also has the same effects as the embodiment shown in FIG.

上述の如く構成された非単結晶層3にレーザ等
へのエネルギー線を照射して広い範囲に渡つて順
次走査し、非単結晶層3を単結晶化するようにな
される。勿論単結晶上にアクテブデバイスを配設
する。本発明は叙上の如く構成させたのでエネル
ギー線の照射によつて非単結晶層3のシリコン内
に熱膨張係数の差による応力歪は生じない
(SiO2層6が薄いため)、更にシリコン基板1と
非単結晶層3との間の静電容量を小さく出来るの
でスピードの早いアクテブデバイスを得ることが
出来、且つ広い範囲に渡つてエネルギー線で非単
結晶化することが出来る特徴を有するものであ
る。
The non-single-crystal layer 3 configured as described above is irradiated with energy beams from a laser or the like and sequentially scanned over a wide range to convert the non-single-crystal layer 3 into a single crystal. Of course, active devices are arranged on the single crystal. Since the present invention is configured as described above, stress strain due to the difference in thermal expansion coefficient does not occur in the silicon of the non-single crystal layer 3 due to energy ray irradiation (because the SiO 2 layer 6 is thin). Since the electrostatic capacitance between the substrate 1 and the non-single crystal layer 3 can be reduced, a high-speed active device can be obtained, and it has the characteristics that it can be non-single crystallized over a wide range with energy rays. It is something.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置用基板の断面図、第
2図は本発明の半導体装置用基板の断面図、第3
図は第2図の電気的な等価回路、第4図は本発明
の他の実施例を示す半導体装置用基板の断面図、
第5図は第4図の電気的な等価回路である。 1…基板、2,6…SiO2等の絶縁層、3…非
単結晶層、4…エネルギー線、5…高抵抗シリコ
ン層。
FIG. 1 is a cross-sectional view of a conventional semiconductor device substrate, FIG. 2 is a cross-sectional view of a semiconductor device substrate of the present invention, and FIG.
The figure shows the electrical equivalent circuit of FIG. 2, and FIG. 4 is a sectional view of a semiconductor device substrate showing another embodiment of the present invention.
FIG. 5 is an electrical equivalent circuit of FIG. 4. DESCRIPTION OF SYMBOLS 1... Substrate, 2, 6... Insulating layer of SiO2 etc., 3... Non-single crystal layer, 4... Energy beam, 5... High resistance silicon layer.

Claims (1)

【特許請求の範囲】 1 半導体基板と、該半導体基板上に設けられた
第1の絶縁層と、該第1の絶縁層上に設けられ電
気的に互いに分離された複数の領域からなるノン
ドープ多結晶シリコン層と、該ノンドープ多結晶
シリコン層上に設けられた第2の絶縁層と、該第
2の絶縁層上に設けられエネルギー線により再結
晶化されてなる単結晶層とよりなり、前記第2の
絶縁層を前記単結晶層より十分に薄くしてなると
ともに前記半導体基板、前記第1の絶縁層、前記
ノンドープ多結晶シリコン層、前記第2の絶縁
層、前記単結晶層とによつて基板構造を構成し、
前記単結晶層にアクテイブデイバイスを設けたこ
とを特徴とする半導体装置。 2 (a) 半導体基板上に第1の絶縁層を形成し、 (b) 該第1の絶縁層上に第1のノンドープ多結晶
シリコン層を形成し、 (c) 該ノンドープ多結晶シリコン層上に第2の絶
縁層を形成し、 (d) 該第2の絶縁層上に第2のノンドープ多結晶
シリコン層を形成し、 (e) 該第2のノンドープ多結晶シリコン層にエネ
ルギー線を照射して単結晶層を形成し、 前記第2の絶縁層を前記単結晶層より十分に薄
く形成するとともに、前記(a)〜(e)の工程により半
導体基板構造を形成し、前記単結晶層にアクテイ
ブデイバイスを形成することを特徴とする半導体
装置の製造方法。
[Claims] 1. A semiconductor substrate, a first insulating layer provided on the semiconductor substrate, and a non-doped polyimide comprising a plurality of regions provided on the first insulating layer and electrically isolated from each other. A crystalline silicon layer, a second insulating layer provided on the non-doped polycrystalline silicon layer, and a single crystal layer provided on the second insulating layer and recrystallized by energy rays, The second insulating layer is made sufficiently thinner than the single crystal layer, and the second insulating layer is formed of the semiconductor substrate, the first insulating layer, the non-doped polycrystalline silicon layer, the second insulating layer, and the single crystal layer. to form the substrate structure,
A semiconductor device characterized in that an active device is provided in the single crystal layer. 2 (a) forming a first insulating layer on a semiconductor substrate; (b) forming a first non-doped polycrystalline silicon layer on the first insulating layer; (c) forming a first non-doped polycrystalline silicon layer on the non-doped polycrystalline silicon layer. (d) forming a second non-doped polycrystalline silicon layer on the second insulating layer; (e) irradiating the second non-doped polycrystalline silicon layer with an energy beam; forming a single crystal layer, forming the second insulating layer sufficiently thinner than the single crystal layer, forming a semiconductor substrate structure by the steps (a) to (e), and forming the second insulating layer sufficiently thinner than the single crystal layer; 1. A method for manufacturing a semiconductor device, comprising forming an active device in a semiconductor device.
JP12482280A 1980-09-09 1980-09-09 Semiconductor device Granted JPS5749224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12482280A JPS5749224A (en) 1980-09-09 1980-09-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12482280A JPS5749224A (en) 1980-09-09 1980-09-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5749224A JPS5749224A (en) 1982-03-23
JPH0142126B2 true JPH0142126B2 (en) 1989-09-11

Family

ID=14894958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12482280A Granted JPS5749224A (en) 1980-09-09 1980-09-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5749224A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168651A (en) * 1983-03-15 1984-09-22 Mitsubishi Electric Corp Semiconductor device
JPS63122468A (en) * 1986-11-11 1988-05-26 林原 健 Low frequency treatment device for bathroom
JPH0345739Y2 (en) * 1986-12-31 1991-09-26
JPH01130744U (en) * 1988-02-27 1989-09-05

Also Published As

Publication number Publication date
JPS5749224A (en) 1982-03-23

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