JPH0137049B2 - - Google Patents
Info
- Publication number
- JPH0137049B2 JPH0137049B2 JP59097975A JP9797584A JPH0137049B2 JP H0137049 B2 JPH0137049 B2 JP H0137049B2 JP 59097975 A JP59097975 A JP 59097975A JP 9797584 A JP9797584 A JP 9797584A JP H0137049 B2 JPH0137049 B2 JP H0137049B2
- Authority
- JP
- Japan
- Prior art keywords
- adder
- mod
- output
- input terminal
- carry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59097975A JPS60241331A (ja) | 1984-05-16 | 1984-05-16 | MOD(2n−1)の加算回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59097975A JPS60241331A (ja) | 1984-05-16 | 1984-05-16 | MOD(2n−1)の加算回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60241331A JPS60241331A (ja) | 1985-11-30 |
| JPH0137049B2 true JPH0137049B2 (enrdf_load_stackoverflow) | 1989-08-03 |
Family
ID=14206662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59097975A Granted JPS60241331A (ja) | 1984-05-16 | 1984-05-16 | MOD(2n−1)の加算回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60241331A (enrdf_load_stackoverflow) |
-
1984
- 1984-05-16 JP JP59097975A patent/JPS60241331A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60241331A (ja) | 1985-11-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4953115A (en) | Absolute value calculating circuit having a single adder | |
| JP3244506B2 (ja) | 小型乗算器 | |
| JP3487903B2 (ja) | 演算装置及び演算方法 | |
| KR950015182B1 (ko) | 갈로아 필드 곱셈회로 | |
| JPH0479013B2 (enrdf_load_stackoverflow) | ||
| EP0416869B1 (en) | Digital adder/accumulator | |
| US6546411B1 (en) | High-speed radix 100 parallel adder | |
| JPH0137049B2 (enrdf_load_stackoverflow) | ||
| JPH0519170B2 (enrdf_load_stackoverflow) | ||
| JP2917577B2 (ja) | 演算装置 | |
| CA1314995C (en) | Method and apparatus for decoding reed-solomon code | |
| JP2578482B2 (ja) | 浮動小数点演算器 | |
| JPH11317676A (ja) | 有限フィ―ルドでの任意要素の逆数具現回路 | |
| JPH0137050B2 (enrdf_load_stackoverflow) | ||
| JPH0778748B2 (ja) | ガロア体演算ユニット | |
| JP2991788B2 (ja) | 復号器 | |
| KR100241071B1 (ko) | 합과 합+1을 병렬로 생성하는 가산기 | |
| JPS6229821B2 (enrdf_load_stackoverflow) | ||
| JP2914813B2 (ja) | 誤り訂正復号装置 | |
| SU1179322A1 (ru) | Устройство дл умножени двух чисел | |
| SU1488796A1 (ru) | Устройство для умножения по модулю | |
| JP2546014B2 (ja) | デイジタル信号処理装置 | |
| JPH0642632B2 (ja) | ガロア体上の演算装置 | |
| JPH0285922A (ja) | 演算回路 | |
| JPH03149924A (ja) | 誤り訂正復号装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |