JPH0136138B2 - - Google Patents

Info

Publication number
JPH0136138B2
JPH0136138B2 JP58229418A JP22941883A JPH0136138B2 JP H0136138 B2 JPH0136138 B2 JP H0136138B2 JP 58229418 A JP58229418 A JP 58229418A JP 22941883 A JP22941883 A JP 22941883A JP H0136138 B2 JPH0136138 B2 JP H0136138B2
Authority
JP
Japan
Prior art keywords
input
control
control unit
output
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58229418A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60122452A (ja
Inventor
Kentaro Myoshi
Toyokazu Nagahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22941883A priority Critical patent/JPS60122452A/ja
Publication of JPS60122452A publication Critical patent/JPS60122452A/ja
Publication of JPH0136138B2 publication Critical patent/JPH0136138B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Control By Computers (AREA)
  • Bus Control (AREA)
JP22941883A 1983-12-05 1983-12-05 制御装置 Granted JPS60122452A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22941883A JPS60122452A (ja) 1983-12-05 1983-12-05 制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22941883A JPS60122452A (ja) 1983-12-05 1983-12-05 制御装置

Publications (2)

Publication Number Publication Date
JPS60122452A JPS60122452A (ja) 1985-06-29
JPH0136138B2 true JPH0136138B2 (enrdf_load_stackoverflow) 1989-07-28

Family

ID=16891913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22941883A Granted JPS60122452A (ja) 1983-12-05 1983-12-05 制御装置

Country Status (1)

Country Link
JP (1) JPS60122452A (enrdf_load_stackoverflow)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421229A (en) * 1977-07-19 1979-02-17 Mitsubishi Electric Corp Data fetch system
JPS5476031A (en) * 1977-11-30 1979-06-18 Hitachi Ltd Input/output control system for electronic computer
JPS55154623A (en) * 1979-05-23 1980-12-02 Hitachi Ltd Input and output control system

Also Published As

Publication number Publication date
JPS60122452A (ja) 1985-06-29

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