JPH0136135B2 - - Google Patents
Info
- Publication number
- JPH0136135B2 JPH0136135B2 JP58087772A JP8777283A JPH0136135B2 JP H0136135 B2 JPH0136135 B2 JP H0136135B2 JP 58087772 A JP58087772 A JP 58087772A JP 8777283 A JP8777283 A JP 8777283A JP H0136135 B2 JPH0136135 B2 JP H0136135B2
- Authority
- JP
- Japan
- Prior art keywords
- bit
- memory
- word
- bits
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012937 correction Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000006467 substitution reaction Methods 0.000 claims 2
- 230000008569 process Effects 0.000 description 8
- 239000013598 vector Substances 0.000 description 7
- 238000003491 array Methods 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1024—Identification of the type of error
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/383,640 US4485471A (en) | 1982-06-01 | 1982-06-01 | Method of memory reconfiguration for fault tolerant memory |
US383640 | 1982-06-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58215800A JPS58215800A (ja) | 1983-12-15 |
JPH0136135B2 true JPH0136135B2 (US08063081-20111122-C00102.png) | 1989-07-28 |
Family
ID=23514037
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58087772A Granted JPS58215800A (ja) | 1982-06-01 | 1983-05-20 | メモリ再構成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4485471A (US08063081-20111122-C00102.png) |
EP (1) | EP0095669B1 (US08063081-20111122-C00102.png) |
JP (1) | JPS58215800A (US08063081-20111122-C00102.png) |
DE (1) | DE3380644D1 (US08063081-20111122-C00102.png) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4584682A (en) * | 1983-09-02 | 1986-04-22 | International Business Machines Corporation | Reconfigurable memory using both address permutation and spare memory elements |
US4729117A (en) * | 1985-03-20 | 1988-03-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JPH071640B2 (ja) * | 1987-06-03 | 1995-01-11 | 三菱電機株式会社 | 半導体記憶装置の欠陥救済装置 |
US4943966A (en) * | 1988-04-08 | 1990-07-24 | Wang Laboratories, Inc. | Memory diagnostic apparatus and method |
JP2617026B2 (ja) * | 1989-12-22 | 1997-06-04 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 障害余裕性メモリ・システム |
US5155844A (en) * | 1990-02-14 | 1992-10-13 | International Business Machines Corporation | Background memory test during system start up |
IT1284244B1 (it) * | 1996-08-05 | 1998-05-14 | Texas Instruments Italia Spa | Sistema per produrre moduli di memoria simm utilizzando chip di memoria aram e per il loro collaudo |
US5809043A (en) * | 1996-10-08 | 1998-09-15 | Ericsson Inc. | Method and apparatus for decoding block codes |
DE10137332B4 (de) * | 2001-07-31 | 2014-11-06 | Qimonda Ag | Verfahren und Anordnung zur Ausgabe von Fehlerinformationen aus Halbleitereinrichtungen |
US6773083B2 (en) | 2001-08-29 | 2004-08-10 | Lexmark International, Inc. | Method and apparatus for non-volatile memory usage in an ink jet printer |
US7065697B2 (en) * | 2003-07-29 | 2006-06-20 | Hewlett-Packard Development Company, L.P. | Systems and methods of partitioning data to facilitate error correction |
US7051265B2 (en) * | 2003-07-29 | 2006-05-23 | Hewlett-Packard Development Company, L.P. | Systems and methods of routing data to facilitate error correction |
US20070277083A1 (en) * | 2004-04-14 | 2007-11-29 | Koninklijke Philips Electronics, N.V. | Data Handling Device That Corects Errors In A Data Memory |
US7272774B2 (en) * | 2004-04-16 | 2007-09-18 | Kingston Technology Corp. | Extender card for testing error-correction-code (ECC) storage area on memory modules |
US7577890B2 (en) | 2005-01-21 | 2009-08-18 | Hewlett-Packard Development Company, L.P. | Systems and methods for mitigating latency associated with error detection and correction |
US7900100B2 (en) * | 2007-02-21 | 2011-03-01 | International Business Machines Corporation | Uncorrectable error detection utilizing complementary test patterns |
EP2063432B1 (de) * | 2007-11-15 | 2012-08-29 | Grundfos Management A/S | Verfahren zum Prüfen eines Arbeitsspeichers |
TW200947450A (en) * | 2008-05-09 | 2009-11-16 | A Data Technology Co Ltd | Storage system capable of data recovery and method thereof |
DE102018126051A1 (de) * | 2018-01-12 | 2019-07-18 | Taiwan Semiconductor Manufacturing Co. Ltd. | Neuartige Speichervorrichtung |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52124826A (en) * | 1976-04-12 | 1977-10-20 | Fujitsu Ltd | Memory unit |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3644902A (en) * | 1970-05-18 | 1972-02-22 | Ibm | Memory with reconfiguration to avoid uncorrectable errors |
US3897626A (en) * | 1971-06-25 | 1975-08-05 | Ibm | Method of manufacturing a full capacity monolithic memory utilizing defective storage cells |
US3781826A (en) * | 1971-11-15 | 1973-12-25 | Ibm | Monolithic memory utilizing defective storage cells |
US3814922A (en) * | 1972-12-01 | 1974-06-04 | Honeywell Inf Systems | Availability and diagnostic apparatus for memory modules |
US3812336A (en) * | 1972-12-18 | 1974-05-21 | Ibm | Dynamic address translation scheme using orthogonal squares |
US3906200A (en) * | 1974-07-05 | 1975-09-16 | Sperry Rand Corp | Error logging in semiconductor storage units |
JPS5528160B2 (US08063081-20111122-C00102.png) * | 1974-12-16 | 1980-07-25 | ||
DE2538579B2 (de) * | 1975-08-29 | 1977-09-29 | Verfahren zum ermoeglichen des einsatzes von teilfunktionsfaehigen halbleiter-speicherbausteinen in einem arbeitsspeichermodul und anordnung zu seiner durchfuehrung | |
US4064558A (en) * | 1976-10-22 | 1977-12-20 | General Electric Company | Method and apparatus for randomizing memory site usage |
-
1982
- 1982-06-01 US US06/383,640 patent/US4485471A/en not_active Expired - Lifetime
-
1983
- 1983-05-19 EP EP83104965A patent/EP0095669B1/en not_active Expired
- 1983-05-19 DE DE8383104965T patent/DE3380644D1/de not_active Expired
- 1983-05-20 JP JP58087772A patent/JPS58215800A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52124826A (en) * | 1976-04-12 | 1977-10-20 | Fujitsu Ltd | Memory unit |
Also Published As
Publication number | Publication date |
---|---|
EP0095669A2 (en) | 1983-12-07 |
DE3380644D1 (en) | 1989-11-02 |
US4485471A (en) | 1984-11-27 |
JPS58215800A (ja) | 1983-12-15 |
EP0095669B1 (en) | 1989-09-27 |
EP0095669A3 (en) | 1987-06-16 |
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