JPH01321545A - Bus state control circuit - Google Patents

Abstract

PURPOSE:To secure the recovery time adaptive to various systems without deteriorating the performance of a microprocessor by delaying the next bus cycle only in the case the continuous accesses are given to the elements of the same type or to the external resources and at the same time the recovery time is needed. CONSTITUTION:The state for security of the recovery time is put into a bus state sequencer of a processor only when the input/output bus accesses are continuous. Then an IOWAIT signal is inputted to show the delay of the start of a bus cycle. This IOWAIT signal is active only in the case an input/output control IC to which the processor has an access does not satisfy the recovery time. Then the IOWAIT signal delays the start of the bus cycle and secures the recovery time of said control IC that had an access. Thus the connection is possible between the elements having the large recovery time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus state control circuit, and particularly to a bus state control circuit that controls access to an input/output control IC or main memory by a microprocessor.

[Conventional technology]

Conventionally, when a microprocessor accesses an input/output control IC such as a communication control IC or a magnetic disk control IC, the input/output control IC is accessed using an input/output instruction, and the instruction is used to access the input/output control IC continuously. Even when the same input/output control IC is accessed by the microprocessor, the operating frequency of the microprocessor is low and the seven-step operation of the instructions always falls into the input/output access range, so the recovery time of the input/output control IC is shortened. The amount of time that must be left before the next access starts has never been a problem.

Currently, as the degree of integration of L8I improves, there are microprocessors that are approaching the performance and functionality of Mozuni computers and general-purpose medium-sized computers.

In particular, in terms of element technology, improvements in operating frequency and in terms of architecture include the introduction of pipeline structures.

As performance improves in architecture, the proportion of accesses outside the microprocessor, the so-called bus access rate, has become extremely high.

In other words, due to the pipeline structure, processes that were performed sequentially are now executed in parallel.

Here, the big line structure will be briefly explained.

The pipeline structure mainly consists of independent units with the following functions:

■ A unit that controls instruction fetch ■ A unit that decodes instructions ■ A unit that calculates operand addresses ■ A unit that transfers data to and from memory and input/output devices ■ A unit that executes instructions Each unit from ■ to ■ above is independent. and are running in parallel. Bus access is performed by the data transfer unit (2) in response to an instruction fetch request from the unit (2) or an access request for operand data from the unit (2) or the unit (2). ) is done through mediation.

Therefore, when accessing operands in a pipeline structure, the operands required for the instruction executed after the instruction at the instruction execution level are read, and the operands included in the instruction completed at the instruction execution level are written. It will be done.

For this reason, if input/output instructions are executed consecutively to the same output control IC, it is possible that the ninth bus cycle for accessing the input/output control IC may occur consecutively. However, a problem arose that the input/output control 1C recovery time could not be guaranteed. Furthermore, similar problems may arise when not only the same person's output control IC but also a memory element such as an instant access RAM is accessed continuously.

Therefore, in recent years, in order to guarantee recovery time, microprocessors are now using buses for input/output or memory.
When the cycles are continuous, a method has been adopted in which a state is set to ensure recovery time and the start of the next bus cycle is delayed.

First, when input/output instructions are executed continuously in a microprocessor, as shown in the typing chart for external access shown in Figure 21, the strobe signal DS is a signal for reading or writing data, and while active, the access time is The recovery time is the period from when the IC becomes inactive until it becomes active again to access the input/output control IC. Note that Ti, TI, T2, T3, and TR are respectively in an idle state in which no external access is performed, a first state in which information for distinguishing between idle information and access information is output, and an access strobe signal is activated. A second state in which the access is started when the access strobe signal becomes inactive, a third state in which the access ends when the access strobe signal becomes inactive, and a state for securing recovery time are shown.

The operation of this microprocessor will be explained using the state transition diagram of FIG. 22 when input/output instructions are executed continuously. First, it is assumed that the bus state Ti is at 9. When the access request signal ACRE becomes active, the state changes from TI to T2 and from T2 to T3 in order to guarantee the access time of the input/output control IC. If the access request signal ACRBC is inactive in the T3 state, the state transitions to the Ti state. Access request signal ACR
BC is active and I10 access signal l0
If both AC and the signal PIO C indicating whether the previous access was to the main memory or to the input/output control ICE are active, a transition is made to state T for securing recovery time. After repeating the TR state several times, it transitions to the T1 state.

Next, when the same input/output control IC is successively accessed by the microprocessor, the timing chart shown in FIG. 21 will also occur. Here, continuous access to an input/output control IC is taken as an example, but the same applies to a memory that requires recovery time. The operation of this microprocessor will be explained using the state transition diagram of FIG. 23 when input/output instructions are executed continuously. First, it is assumed that the bus state is Ti. When the access request signal ACRE becomes active, the state changes from Tl to T2 and from T2 to T3 in order to guarantee the access time of the input/output control IC. If the access request signal ACRE is inactive in the T3 state, the state transitions to the Ti state. If the access request signals ACR and EC are active, and the input/output access signal 10AC and the signal PIOAC indicating whether the previous access was to the input/output control IC are both active, a state for securing recovery time is established. Transition to TR. After repeating the TR state several times, it transitions to the T1 state.

[Problem to be solved by the invention]

In the conventional bus state control circuit described above, a recovery time is always secured when accesses for input/output are made consecutively, and the recovery time also depends on various input/output control ICs and memories. guaranteed,
Moreover, since it is fixed, there is a problem that a system that does not require much recovery time cannot fully demonstrate its performance. On the other hand, there is also the problem that the recovery time is not satisfactory for input/output control ICs and memories which are large and require a long recovery time.

Ninth, another way to ensure recovery time is to create software that does not execute input/output commands continuously for input/output control ICs where recovery time is a problem. can give. However, with this method, software must be created taking into account hardware factors such as the microprocessor, its pipeline structure, the degree of parallel execution of instructions, clock frequency, and recovery time for the input/output control IC. Therefore, the burden on software developers increases,
Furthermore, the same program may not run on another system with different hardware elements.

Even if software is created that allows sufficient time between input and output commands to operate on a variety of systems, it will not be able to fully demonstrate its performance on systems that do not require much recovery time.

As mentioned above, in the conventional method, microprocessor,
It is difficult to ensure a recovery time that is suitable for various systems without degrading the performance of the system.

The present invention secures recovery time by delaying the next bus cycle only when the same type of element or external resource is accessed in succession and the element or external resource requires recovery time. The goal is to control the bus state so that

[Means to solve the problem]

The bus state control circuit of the present invention is used in an external access mechanism of a central information processing unit, and includes an access control circuit that generates several states for external access and performs access, and an external access control circuit that requests access to an external access target. an access request means, an access type signal for specifying whether or not the external access request is an access to an input/output device, and a continuous wait request terminal after external access to the input/output device; When external access to the input/output device is performed by the access control circuit, the wait request terminal requests that the next external access be delayed when external access requests to the input/output device are successively received; and when the external access request means makes a next external access request and the next external access is specified as an access to the input/output device by the access type signal, the access control circuit performs the next external access request. The purpose is to delay external access to the input/output device.

Furthermore, the bus state control circuit of the present invention is used in an external access mechanism of a central information processing unit. and an access type indicating the type of the external access target, and a wait request terminal that requests whether or not to delay the start of the access when access to the external access target occurs. , among the access requesting means, there are a plurality of external access targets that can be distinguished by the access type and part of the address information, and one of the external access targets has been successively accessed. , and when the access control circuit performs external access to the external access target, the wait request terminal and the comparison circuit continuously detect external access to the same external access target. When the next external access is requested to be delayed when an access request comes, and the ninth external access request by the external access request means is the same access as the external access target, the access control circuit The object of the present invention is to delay the next external access to the external access target performed by the external access target.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the first invention. In FIG. 1, one embodiment of the first invention is a two-phase lock type bus.
The state control circuit includes a combinational logic circuit 101 (hereinafter referred to as PLA) for determining the next bus state based on the current bus state and an external input signal.

D type pretend.

P-flops (hereinafter referred to as FFs) 105 to 109 use a first clock (hereinafter referred to as PHII) as a clock signal, and each output represents the current bus state. In other words, the output of the D-type FF 105 is in an idle state (Ti),
The output of type FF 106 is in the first state of the bus cycle (T
I), the output of D-type FF 107 is in the second state of the bus cycle (T2), the output of D-type FF 108 is in the third state of the bus cycle (T3), and the output of D-type FF 109 is to ensure recovery time. state (TR).

In the Ti state, the process does not perform external access. The TI state is a state that transitions at the beginning of a bus cycle, in which the access strobe signal becomes active and actual access to the memory element or input/output device is started. In this embodiment, the signal indicating the Tl state, that is, the output signal of the 9DfJFF 106, becomes the starting point of the access strobe signal. This is the state that transitions next to the T2 state and the Ti state. The T3 state is a state to which the T2 state transitions, and the access strobe signal becomes inactive and the access ends.

The D-type FFs 110 to 114 use a second clock signal (hereinafter referred to as PH, 12) as a clock, and are current.

It is a D-type clip-flop for delaying the state, and each output is input to PLAIOI.

Further, a signal 102 input to PLAIOI is a signal indicating an access request (hereinafter abbreviated as ACEC), and a signal 103 indicates that the access request signal ACREC is related to input/output when it is active. I10
The access signal l0AC, the signal 104 is the previous I1
0 access signal l0AC to 1 with D-type FF115, 116
The signal PIOAC, which is delayed by a clock, determines whether the previous access was to the main memory or whether the input/output control I
This is a signal indicating whether it is for CE.

Signal 120 is a signal (hereinafter referred to as 10WIT signal) indicating whether a recovery time is required for access. PLAIOI receives these input signals.
Determine the next bus state. Figure 2 is PLAIOI
This is the truth table of

Next, the operation will be explained with reference to FIG. Note that the Roman numerals shown in parentheses below correspond to the numbers of each item in FIG. First of all, Ti is the bus state.
Suppose that the state is (1).

In this state, when the ACREQ signal 102 becomes active, a transition is made to the T1 state (El). It then transitions to the T2 state l). Next, transition to T3 state (IV)
. If the ACREQ signal 4102 is inactive in the T3 state, the state shifts to the Ti state (■). On the other hand, when the access request signal ACRE is active, the signal P
IOAC is inactive, that is, the current bus cycle is for memory, or I10 access signal l0AC is inactive, and t9 Even if the current bus cycle is for input/output, the next bus cycle is for memory. whether the signal 10AC and the signal P
Even if both IOACs are active, if the l0WAT signal is inactive and l) consecutive bus cycles are for input/output and there is no need to secure the 4-return time, the bus transitions to the T1 state (V, Vl, ■).

In state T3, if consecutive bus cycles are for input/output, the access signal PIOAC and I10 access signal l0AC are both active, and if the IOWAIT signal is active, recovery time is secured. Transition to state TR for ([
). Transition from TR state to T1 state unconditionally (X)
.

FIG. 3 shows the above operation in a state transition diagram.

FIG. 4 is a timing chart when input/output accesses and memory accesses that require a recovery time are consecutive. From the T3 state of the I/O access cycle, I
A transition to the T1 state of the memory access cycle is shown regardless of the value of the OWA IT signal.

Figure 5 Beam Coverage - Need to secure time, Tsum I OW
This is a tying chart when the AIT signal is activated and input/output access is continued.

It is shown that there is a transition from the T3 state of the first input/output access cycle to the TR state for securing recovery time, and then to the Tl state of the next input/output access cycle. As explained above, in this example,
For input/output control ICs that do not require recovery time [7], there is no need to secure recovery time;
This eliminates the need for deterioration in processor performance.

Next, in another embodiment of the first invention, using the configuration example of the bus state control circuit shown in FIG. 1, FIG. 6 shows a truth table of PLAIOI for determining the next bus state.

The state transitions from FIG. 6 to (I) to (X) are the same as in the embodiment of the first invention. The operation in the TR state will be explained. In the TR state, if IOW
If the human IT signal is active, it remains in the TR state (X
).

In the TR state, if the I OWA I T signal is inactive, a transition is made to the T1 state (XI').

FIG. 7 shows the above operation in a state transition diagram.

Next, a configuration example of a computer system to which another embodiment of the first invention shown in FIG. 8 is applied will be explained.

Microprocessor 801 is a central information processing unit according to another embodiment of the invention. When the microprocessor 801 accesses the input/output control IC 807, it first outputs the address of the input/output space to be accessed to the address path 802, and also outputs the M/IO signal 803 indicating that the access is to the input/output space. becomes low level.

Decoder circuit 808 connects address bus 802 to M/I
It inputs the O signal 803, decodes that it is an access to the input/output control IC 807, and makes its output 809 active. This signal 809 is input/output control IC 8
07 select signal.

Next, the microprocessor 801 input/output control IC 807
When reading, the RDSTB signal 804 becomes active, and when writing, the W8TB signal 805 becomes active. These signals 804 and 805 cause the input/output control IC 807 to input or output data.

When either the RD8TB signal 804 or the WR8TB signal 805 becomes active, the output of the OR gate 810 becomes active. At this point, the output of the decoder 809 remains active, so the output of the AND gate 811 becomes high level. The output of AND gate 811 is connected to the input of timer 812.

The timer 812 detects the falling edge of the input signal,
From that point on, the output 813- is kept at a high level for a certain period of time. The timer output 814 and the output of the decoder 809 are passed through an AND gate 814 to the microprocessor 80.
It is connected to the I OWA IT terminal 806 of No. 1.

Next, the operation of another embodiment of the first invention described above will be explained.

If the microprocessor 801 accesses the input/output control IC 807 at a certain point, the timer 812 starts counting time, and the microprocessor 801 starts the next access before the output 813 of the timer 812 becomes low level. If the access is the same input/output control IC
, AND gate 814 goes high. In other words, since the values of the address bus 802 and M/IO signal 803 do not change, the output 809 remains high, and the output 813 of the timer 812 remains high.
Since the level is high, the AND gate 814 becomes high level. This signal is an I
OWA I T signal 806, microprocessor 801 is 8TB signal 804 or WR8TB
Activation of signal 805 is postponed. When the timer outputs a low level after a predetermined period of time, the l0WAIT signal 806 becomes inactive and the microprocessor 801 activates the RD8TB signal 805 to access the input/output control IC.

Therefore, by setting a time sufficient for the timer 812 to satisfy the recovery time of the input/output control IC 807, the recovery time of the input/output control IC 807 can be maintained no matter what order the microprocessor 801 accesses the outside. can be met.

Another embodiment of the first invention is a tying chart shown in FIG. Assuming that the two accesses in FIG. 9 are to the same element, the transition from the fall of the access strobe signal in the first access to the rise of the access strobe signal in the second access
This is the recovery time for the element accessed at t.

Therefore, by extending the input of the 10WAIT signal, the necessary glue recovery time can be secured.
It becomes possible to connect any element.

Therefore, in a computer system using a processor implementing the first invention, the recovery time can be satisfied without deteriorating the performance of the processor, and when a dangerous element is connected, a small amount of hardware is added to the element. This allows you to get the best performance.

This figure shows the position of the control circuit in a microprocessor with a pipeline structure. In Figure 11, Uni, )
(EXU) zOt executes the instruction and unit (BCU)
) 202 performs data transfer with memory and input/output devices. Units) EXU and BCU transfer data using address bus 203 and data bus 205,
Uni,) BCU is a 7 dress bus 204. ! - Data is transferred to and from memory and input/output devices via the data bus 206.

When there is an access request, the BCU reads or writes data on the address bus to the memory or input/output device. Between unit BCU and EXU, the data read from the outside by unit E
The unit BCU transfers the data to the XU or writes the data processed by the EXU to the outside. Data access of the unit ECU is performed by activating a bus cycle by the bus state control circuit.

A two-phase lock type bus which is an embodiment of the second invention.
The state control circuit is shown in FIG. In FIG. 1O, a combinational logic circuit 151 is a circuit (hereinafter abbreviated as PLA 151) for determining the ninth bus state based on the current bus state and an external input signal. 155 to 159 are D-type flip-flops using the first clock signal (hereinafter abbreviated as PHII), and each output represents the current bus state. Tsumufi, output of 155 is in idle state (Ti), output of 156 is in bus/
In the first state (TI) of the cycle, the output of 157 is connected to the bus
The output of the second state (T2) of the cycle 158 indicates the third state (T3) of the bus cycle, and the output of 109 indicates the state (TR) for ensuring recovery time. In the Ti state, the processor does not perform external access.

The Tl state is a state that transitions at the beginning of a bus cycle, and when the access strobe signal becomes active, actual access to the memory or input/output device begins. In this embodiment, the signal indicating the Tl state, that is, the D-type free,
The output signal of flop 156 is the starting point for the access strobe signal. The T2 state is a state to which the state transitions next after the Tl state.

The T3 state is a state to which the T2 state transitions, and the access ends when the access strobe signal becomes inactive. 160 to 164 are the second clock signal (hereinafter abbreviated as PH1z), and the DW flip-flop and push switch for delaying the current state, each output is input to PLA 151. has been done. Also, P.L.
A signal 152 input to A151 is a signal indicating an access request (hereinafter abbreviated as ACRE), and a signal 153 is
When the access request signal AC)t, Ec is active, it is an access signal MREQ indicating that it is related to a memory, and the signal 154 is an access signal MREQ indicating that it is related to a memory.
This is a signal PMREQ delayed by one clock in the EQtD type 7 lip flow, block 165.degree. 166, and is a signal indicating whether the previous access was to the memory or to the input/output control IC. The WAIT generation circuit 170 outputs a WAIT request signal when the same element is successively accessed. This WAIT generation circuit 170 is connected to the address bus 117 and the TI status signal 16.
B and an external signal 169 (hereinafter referred to as WAITRQ) indicating whether a recovery time is required for access.
The signal 131 is an output signal from the WAIT generation circuit 170 (hereinafter this output signal will be referred to as MI
(abbreviated as WAIT signal). WAIT generation circuit 1
The internal circuit of 70 is shown in FIG. In Figure 12,
Signal 131 holds the address on address bus 167 and is latched at PH/2 of cycle T1. The comparator 302 is a comparator that compares part of the address, and the address latched by the signal 131 and the address latched by the signal 131.
The addresses on the address bus 117 are compared. -1,
The currently valid address is compared with the previously accessed address to detect whether the same memory or input/output control IC is being accessed. AND gate 303 outputs the output signal 304 from the comparator and the WAIT signal Q.
It receives a signal 169 as an input, and becomes active when the addresses match and a recovery time is required for access. MIWAIT of Tsuma Shim ND Gate 303
Signal 131 becomes active. M I WA I T
Signal 131 becomes an input signal to PLA 151. P.L.A.
I51 determines the next bus state by these input signals.

FIG. 13 is a directivity table of PLA151.

Next, an embodiment of the second invention will be described with reference to FIG. In addition, the row! shown in parentheses below! The number is 13th
Corresponds to the number of each term in the figure.

First, assume that the bus state is Ti (1). In this state, when the ACREQ signal 152 becomes active, a transition is made to the Ti state (1). Then,
Transition to T3 state (mV).

If the ACREQ signal 152 is inactive in the T3 state, the state shifts to the Ti state (■). - On the other hand, if the access request signal ACRE is active, the signal PM
REQ is inactive, the current bus cycle is not for memory, or the memory access signal M
If REQ is inactive, or if the current bus cycle is to memory but the next bus access is not to memory, signals M_EQ and PME are
Even if Q are both active, if the MIWAIT signal 131 is inactive, that is, there is no need to secure recovery time even if consecutive bus cycles are for the same memory IJK, the state transitions to Tl (V, V
I, Vl), in the T30 state, if consecutive bus
If the cycle is for a memory, if both the access signal PMREQ and the memory access signal MRBQ are active and the MIWAIT signal 131 is active, a transition is made to state TR for securing recovery time (W). From the TR state, there is an unconditional transition to the T1 state (X).

FIG. 14 shows the above operation in a state transition diagram.

Memo IJ for different pages and pages that require recovery time
When access to K is continuous, the timing chart shown in FIG. 15 is obtained. From the T3 state of the memory access cycle, regardless of the value of the W person ITRQ signal,
The transition to the Tl state for different memory access cycles is shown.

Furthermore, it is necessary to secure recovery time.
When the signal is activated and memory accesses of the same program are performed consecutively, the timing chart shown in FIG. 17 is obtained. It is shown that there is a transition from the T3 state of the first memory access cycle to the TR state for securing recovery time, and then to the T1 state of the next memory access cycle nine seconds later.

The comparator used in the embodiment of the second invention can detect continuous access to any memory in units of programs by varying the number of bits of the addresses to be compared. FIG. 24 shows an example of the variable length comparator. The word length of the address to be compared is in register 1.
Based on the value set in 41, the address decoder 142
is specified by masking out the bits that are not compared. The output of the decoder with respect to the set value of the register 141 is shown in FIG. Relative softness is performed when the output of the decoder is "O".

As described above, in the embodiment of the second invention, recovery time is not wasted or secured for input/output control ICs or memories that do not require recovery time. Furthermore, even when accessing the dynamic RAM that requires securing a recovery time, if the access is not to the same professional, different dynamometer, or printer λM, there is no need to secure the recovery time.

Next, in another embodiment of the second invention, using the configuration example of the bus state control circuit shown in FIG. 10, the truth table of PLAI 51 for determining the next bus state is shown in FIG. . As shown in FIG. 18, the state transitions from (1) to (W) are the same as in the second embodiment. The operation in the TR state will be explained. In the TR state, if the WAITRQ signal is active, it remains in the ITR state with the MIWAIT signal active (X). In the TR state, if the WAITRQ signal is inactive, a transition is made to the Tl state (Xl).

FIG. 19 shows the above operation in a state transition diagram.

Next, a configuration example of a combination system to which another embodiment of the second invention shown in FIG. 17 is applied will be described.

A microprocessor 801 is a central information processing unit according to an embodiment of the second invention.几AM810-812 is
It is a 64-byte dynamic RAM. The microprocessor 801 accesses the dynamic RAM 810 at addresses 0-F of the 1M byte main memory space.
This is a case where there is a request to access the address of FFFh. First, the address of the memory space to be accessed is output to the address bus 802, and the M/IO signal 803, which indicates that the memory space is being accessed, goes low. Decoder circuit 808 inputs address bus 802 and M/IO signal 803, decodes that it is an access to dynamic RAM 810, and makes its output 809 active. This signal 809
becomes a select signal for the Dyna Z-'J RAM 810. Next, the microprocessor 801 transfers to the RAM 8.
When reading 10, the RD8TB signal 804 becomes active, and when writing, the WR8TB signal 805 becomes active. These signals 804 and 805 cause the dynamic RAM 810 to take in and output data. 8TB signal 804 or WR8TB signal 8
05 becomes active (OR game) 808
output becomes active. The output of OR gate 807 is connected to the timer 8120 input. The timer 812 detects a falling edge of the input signal and keeps its output 813 at the I level for a certain period of time from that point. Output 813 is WAITRQ of microprocessor 801
Connected to terminal 806.

Next, the operation of another embodiment of the second invention described above will be explained.

Assume that at a certain point in time, the microprocessor 801 accesses the dynamic relay AM 810, the timer 814 starts counting time, and the microprocessor 801 starts the next access before the output 813 of the timer 814 becomes low level. .

If the access is to the same Dynahack AMK, the output signal 813 is sent to the microprocessor 8
Since the WAITRQ signal 806 is for 01, the internal signal MIWAIT becomes active, and the microprocessor 801 receives the RD8TB signal 804 or WR8TI.
Activation of I signal 805 is postponed. When the timer outputs a low level after a predetermined period of time, the WAITRQ signal 806 becomes inactive.
The microprocessor 801 activates the RD8TB signal 804 or the WR8TB signal 805 to
Access Furi AM.

Therefore, for the timer 814, the Dyna I Tsuku Ordinary M8
Microprocessor by setting the table time enough to satisfy the 10 glue coverage times. 801, no matter what order you access the external
10 recovery times can be reduced to a full nine. however,
The timer needs to be a retriggerable timer such that if the trigger from the OR gate 810 occurs while the timer is running, the timer will be restarted.

FIG. 20 is a timing chart of another embodiment of the second invention. Assuming that the two memory accesses in FIG. 20 are to the same dynamic AM, the falling edge of the access strobe signal in the first access will be the rising edge of the access strobe signal in the second access. Dynaba accessed with pt,
This is the recovery time for RAMK.

Therefore, by extending the input of the W-person IT-Q signal, the necessary coverage time can be secured.
It becomes possible to connect any element.

Therefore, in a computer system using the processor of the other embodiment of the second invention, when connecting an element that cannot satisfy the recovery time without causing a decrease in processor performance, a small amount of hardware is added to that element. This allows you to get the best performance.

〔Effect of the invention〕

As explained above, the first invention is based on the processor bus.
Input a signal (IOWAIT signal) indicating that the start of the next bus cycle is delayed by inserting a state to ensure recovery time only when input/output bus accesses are continuous in the state sequencer. be able to.

This I OWA I T signal is activated only when the I/O control IC that the processor is trying to access has not satisfied its recovery time, thereby instructing the processor to start a bus cycle. delay,
By ensuring recovery time for the accessed input/output control IC, it is possible to connect elements that require a long recovery time without degrading the performance of the processor.

Furthermore, the second invention is capable of inserting a ninth state into the bus state sequencer of the processor to ensure recovery time and delaying the start of a subsequent bus cycle when bus accesses to the same element occur continuously. can. If the external element that the processor attempts to access does not satisfy its recovery time, the input signal WAITRQ to the processor is activated, and when successive accesses to the same element are detected, a bus cycle is started. It is possible to secure recovery time for the accessed element. Improve the performance of the handle, processor, and
This has the effect of making it possible to connect elements with a long recovery time without causing damage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the first invention, FIG. 2 is a diagram showing a combinational logic circuit truth table in an embodiment of the invention, and FIG. 3 is an embodiment of the first invention. FIGS. 4 and 5 are transition diagrams showing the states of . Fig. 7 is a state transition diagram showing another embodiment of the first invention, and Fig. 8 shows an example of the configuration of a nine-component system applying the process implementing the first invention. 9 is a diagram showing a timing chart of another embodiment of the first invention, FIG. 10 is a circuit diagram showing an embodiment of the second invention, and FIG. 11 is a diagram showing a timing chart of another embodiment of the first invention. A configuration diagram showing one embodiment, FIG. 12 is a diagram showing a comparison circuit of an embodiment of the second invention, and FIG. 13 is a diagram showing a truth table of a combinational logic circuit in an embodiment of the second invention. , FIG. 14 is a state transition diagram showing an embodiment of the second invention, FIGS. 15 and 16 are tieing charts showing an embodiment of the second invention,
FIG. 17 is a circuit diagram showing an example of a copy/copy one-shot configuration using a processor embodying the second invention, and FIG. 18 is a diagram showing a truth table of a combinational logic circuit in an embodiment of the present invention. , FIG. 19 is a state transition diagram showing another embodiment of the second invention, FIG. 20 is a diagram showing a timing chart of another embodiment of the second invention, and FIG. 21 is a state transition diagram showing another embodiment of the second invention. FIG. 22 and FIG. 23 are diagrams showing state transitions regarding external access of a conventional microprocessor. FIG. 24 is a comparison circuit of another embodiment of the second invention. Detailed view showing 2nd
FIG. 5 is a diagram showing a truth table of another embodiment of the second invention. 101.151...Combinational logic circuit, 105
~114,155~164...D type flip
Flo, P, 801... Processor, 807°.
...Input/output control IC, 808...Decoder circuit, 810.°. -OR gate, 811...AND gate, 81
2...Timer, 814...AND game). Agent Patent Attorney Susumu Uchihara Z Shusaku 3 Swordsmanship 6 z Kabuto '71Zl Kotobuki j7 Sword No. J2 Ward゛301 蝬 14 fig.lδ m fear 1q Kaito 22 r: JJ Kan 23 fig. 24

Claims (2)

[Claims] (1) In the external access mechanism of the central information processing unit,
an access control circuit that generates several states for external access and performs access; an external access request means that requests access to an external access target; and whether the external access request is for access to an input/output device. an access type signal that specifies whether or not to access the input/output device; and a wait request terminal that requests whether or not to delay the start of the access when successive accesses to the input/output device occur after an external access to the input/output device. and when external access to the input/output device is performed by the access control circuit, delaying the next access when external access requests to the input/output device are successively received by the wait request terminal. when the next external access request is made by the external access requesting means, and the next external access is specified as an access to the input/output device by the access type signal, the access control circuit performs the following: A bus state control circuit that delays a next external access to the input/output device. (2) In the external access mechanism of the central information processing unit,
An access control circuit that generates several states for external access and performs access; and an external access request that requests access to an external access target using address information and an access type indicating the type of the external access target. means, a wait request terminal for requesting whether or not to delay the start of said access when access to said external access target occurs, and said access request means distinguished by said access type and part of said address information. a plurality of external access targets that can be accessed, and a comparison circuit that detects that one of the external access targets has been successively accessed;
When external access to the external access target is performed by the access control circuit, when an external access request to the same external access target is successively received by the wait request terminal and the comparison circuit, the next external access is performed by the access control circuit. and when there is a next external access request by the external access request means and the access is the same as the external access target, the next external access to the external access target performed by the access control circuit is delayed. A bus state control circuit characterized by delaying the bus state.