JPH01316985A - Generation of semiconductor laser - Google Patents

Generation of semiconductor laser

Info

Publication number
JPH01316985A
JPH01316985A JP14879988A JP14879988A JPH01316985A JP H01316985 A JPH01316985 A JP H01316985A JP 14879988 A JP14879988 A JP 14879988A JP 14879988 A JP14879988 A JP 14879988A JP H01316985 A JPH01316985 A JP H01316985A
Authority
JP
Japan
Prior art keywords
layer
semiconductor laser
cladding layer
mask pattern
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14879988A
Other languages
Japanese (ja)
Inventor
Susumu Asata
麻多 進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14879988A priority Critical patent/JPH01316985A/en
Publication of JPH01316985A publication Critical patent/JPH01316985A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease a leakage current so as to obtain a semiconductor laser capable of operating at a high speed by a method wherein a process is performed without exposing an active layer to air so as to prevent an n-growth layer from forming beside an active later region. CONSTITUTION:A mask pattern 13 is provided onto an n-type InP clad layer 10, an InGaAsP active layer 11, and a first P-type InP clad layer 12 which have been laminated, which is subjected to a laboratory etching and then a semi-insulating current blocking layer 14 is grown inside and over the etched groove. The pattern 13 is removed and a dielectric insulating film 16 pattern formed of SiO2 is provided in place of it, and a Zn doped second P-type clad layer 15 is grown until the upside of an element becomes even. Lastly, electrodes 17 and 18 are provided to both the front and rear of the element. By these processes, a leakage current can be decreased and a semiconductor laser operable at a high speed can be obtained.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は光通信や光情報処理に用いられる半導体レーザ
の製造方法詳しくは半絶縁性電流阻止層の形成に関する
DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor laser used for optical communications and optical information processing, and more particularly to the formation of a semi-insulating current blocking layer.

(従来の技術とその問題点) 半導体レーザは光通信や光情報処理のキーとなるデバイ
スであり、無効もれ電流が少なく高速動作できかつ製作
が容易なことが要請されている。
(Prior Art and its Problems) Semiconductor lasers are key devices in optical communications and optical information processing, and are required to have low reactive leakage current, operate at high speed, and be easy to manufacture.

無効もれ電流が少なく高速動作できがつ製作が容易であ
る要請に答えるものとして、半絶縁性電流阻止層を活性
領域両脇に埋め込んだ半導体レーザが期待されている。
Semiconductor lasers in which semi-insulating current blocking layers are embedded on both sides of the active region are expected to meet the demands for low reactive leakage current, high speed operation, and easy manufacturing.

そのような半導体レーザの従来例は、エレクトロニクス
・レターズ22巻1986年1214頁(Electr
on、 Lett、 gλ1214(1986))に記
載されている。第2図はこの素子の従来の製造方法の工
程概略図である。すなわち、第2図(I)のように、n
形InPクラッド層10. InGaAsP活性層11
、p形InPクラッド層からなるダブルへテロ構造のウ
ェハ試料上にストライプ状のマスクパターン13を設は
エツチングを行なってメサ状の活性領域を形成する第1
の工程と、第2図(II )のように半絶縁性電流阻止
層14を気相成長法により活性領域の両脇に埋め込む第
2の工程とからなっている。この従来の素子製造方法で
は、活性領域幅が所定値でかつ活性領域の両脇のもれ電
流が小さい素子を常に作製することが容易でなかった。
A conventional example of such a semiconductor laser is described in Electronics Letters, Vol. 22, 1986, p. 1214 (Electr.
on, Lett, gλ1214 (1986)). FIG. 2 is a schematic process diagram of a conventional manufacturing method for this element. That is, as shown in FIG. 2(I), n
InP type cladding layer 10. InGaAsP active layer 11
In the first step, a striped mask pattern 13 is formed on a double heterostructure wafer sample consisting of a p-type InP cladding layer and etched to form a mesa-shaped active region.
and a second step of embedding semi-insulating current blocking layers 14 on both sides of the active region by vapor phase growth as shown in FIG. 2(II). With this conventional device manufacturing method, it is not easy to always produce devices with a predetermined active region width and a small leakage current on both sides of the active region.

すなわち、従来の製造方法では、p形りラッド層12の
膜厚が大きいため第1の工程のエツチングによる寸法制
御が必ずしも容易でなかった。また、従来方法では第1
の工程後第2の工程に至るまで活性領域の両脇が大気中
に露出しているため、変成層などが形成されて表面再結
合電流による大きなもれ電流が生ずるという問題があっ
た。またこれを避けるため、成長炉内で実験室中(in
 5itu)エツチングあるいはメルトバックを用いて
埋込層14を成長させることも従来試みられていたが、
このとき、活性領域幅の寸法制御が更に悪くなる問題が
あった。
That is, in the conventional manufacturing method, since the thickness of the p-type rad layer 12 is large, it is not necessarily easy to control the dimensions by etching in the first step. In addition, in the conventional method, the first
Since both sides of the active region are exposed to the atmosphere after the second step until the second step, there is a problem in that a metamorphosed layer is formed and a large leakage current is generated due to surface recombination current. In addition, to avoid this, in the laboratory (in-house) inside the growth reactor.
5) Although attempts have been made to grow the buried layer 14 using etching or meltback,
At this time, there was a problem that the dimensional control of the active region width became even worse.

本発明の目的は、゛上記の従来素子製造方法における問
題点を除去し、もれ電流が少なく高速でかつ活性領域幅
の制御の容易な半導体レーザの製造方法を提供すること
である。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor laser that eliminates the problems in the conventional device manufacturing method described above, has low leakage current, is fast, and allows easy control of the width of the active region.

(問題点を解決するための手段) 本発明の半導体レーザの製造方法は、活性層が下側をn
形半導体クラッド層、上側を第1のp形半導体クラッド
層で挾まれた構造を持つウェハ試料の上にストライプ状
のマスクパターンを設け、前記マスクパターン直下の前
記活性層まで、実験室中(in 5itu)エツチング
を行なった後直ちにエツチング溝内及び溝上に半絶縁性
電流阻止層を成長する第1の工程と、前記マスクパター
ンを除去した前記第1のp形半導体クラッド層の上に第
2のp形半導体クラッド層を選択成長しメサ状電流通電
部を形成する第2の工程を持つことが特徴である。
(Means for Solving the Problems) In the method for manufacturing a semiconductor laser of the present invention, the active layer has an
A striped mask pattern is provided on a wafer sample having a structure in which a p-type semiconductor cladding layer is sandwiched between a first p-type semiconductor cladding layer on the upper side, and a striped mask pattern is provided in a laboratory (in-house) up to the active layer directly under the mask pattern. 5itu) A first step of growing a semi-insulating current blocking layer in and on the etching groove immediately after etching, and a second step of growing a semi-insulating current blocking layer on the first p-type semiconductor cladding layer from which the mask pattern has been removed. It is characterized by having a second step of selectively growing a p-type semiconductor cladding layer to form a mesa-shaped current carrying part.

(発明の作用) 本発明の作用についてInGaAsP/InPレーザを
例にとり図面を用いて説明する。本発明では先ず、第1
図(Ia)のように積層したn形InPクラッド層10
、InGaAsP活性す11、第1のp形InPクラッ
ド層12上にマスクパターン13を設は実験室中(in
 5itu)エツチングを行なった後直ちに第1図(I
b)のように、半絶縁性電流阻止層14をエツチング溝
内及び溝上に成長する。本発明では、活性層11を露出
させずかつマスクパターンを用いてのエツチング後の活
性領域幅の制御が十分可能な程度の膜厚を持った第1の
p形InP7ラツド層12を設け、実験室中(in 5
itu)エツチング工程を実行することで、活性領域幅
の制御性がよくかつ活性層両脇の表面再結合機構による
もれ電流を減少できる作用が得られる。また、半絶縁性
電流阻止層の成長において、従来の気相成長法(VPE
法)では活性領域脇にn−成長21が成長し、電極17
からn−成長層21を経由し、n形りラッド層lOへ直
接流れるもれ電流もあったが、本発明では、この機構に
よるもれ電流も防止することができる。
(Operation of the invention) The operation of the invention will be explained using the drawings, taking an InGaAsP/InP laser as an example. In the present invention, first, the first
N-type InP cladding layer 10 stacked as shown in Figure (Ia)
A mask pattern 13 is provided on the InGaAsP active layer 11 and the first p-type InP cladding layer 12.
Immediately after etching (I
As in b), a semi-insulating current blocking layer 14 is grown in and on the etched trench. In the present invention, a first p-type InP7 rad layer 12 was provided with a thickness sufficient to allow control of the width of the active region after etching using a mask pattern without exposing the active layer 11. In the room (in 5
By performing the etching process, the width of the active region can be controlled well and leakage current due to the surface recombination mechanism on both sides of the active layer can be reduced. In addition, in the growth of semi-insulating current blocking layers, conventional vapor phase epitaxy (VPE) is used.
(method), n-growth 21 grows beside the active region, and electrode 17
Although there was also a leakage current flowing directly from the n-type rad layer IO to the n-type rad layer 21, the present invention can also prevent leakage current due to this mechanism.

以下、本発明の実施例について更に詳しく説明する。Examples of the present invention will be described in more detail below.

(実施例1) 第1図は本発明の実施例を示す工程概略図である。本発
明では、第1図(Ia)のように、硫黄(S)を2×1
018cm=程度ドーピングしたn形InPクラッド層
10の上に波長1.3pm組成で0.1pm厚のInG
aAsP活性層11と、亜鉛(Zn)を約2X1018
cm−3ドーピングした0、211m厚の第1のp形I
nPクラッド層12とを成長したウェハ試料の上にスト
ライプ幅約1.5pmの8102マスクパターンを設け
た。この試料を気相成長(VPE)炉内において通常の
InP成長に用いるInClとP馬ガス雰囲気中におい
てHCIエツチングガスを流し、マスクパターンでおお
われていない部分を活性層11の下端までin 5it
uエツチングを行なった。その後直ちにMCIエツチン
グガスの供給を停止しがわりにFeCl2ガスを送りこ
むことでFeドープInPからなる厚さ3戸mの半絶縁
性電流阻止層14を第1図(Ib)のように成長する第
1の工程を実行した。引続き第2の工程として、第2の
p形InPクラッド層からなるメサ状電流通電部を形成
することを行なった。すなわち第1図(II )のよう
にマスクパターン13を除去しがわりにSiO2からな
る誘電体絶縁膜16パターンを設け、Znを約2×10
18cm−3ドーピングした第2のp形InPクラッド
層を素子上面が平らになるまで成長した。最後に素子の
表・裏画面に電極17.18を設ける通常の工程を経て
半導体レーザを作製した。
(Example 1) FIG. 1 is a process schematic diagram showing an example of the present invention. In the present invention, as shown in FIG. 1 (Ia), sulfur (S) is
0.1 pm thick InG with wavelength 1.3 pm composition on n-type InP cladding layer 10 doped to 0.018 cm
aAsP active layer 11 and zinc (Zn) of about 2×1018
cm-3 doped 0.211 m thick first p-type I
An 8102 mask pattern with a stripe width of about 1.5 pm was provided on the wafer sample on which the nP cladding layer 12 was grown. This sample was placed in a vapor phase epitaxy (VPE) furnace in an InCl and P gas atmosphere used for normal InP growth, and HCI etching gas was passed through it, and the portion not covered by the mask pattern was injected in 5 it up to the lower end of the active layer 11.
U-etching was performed. Immediately thereafter, the supply of MCI etching gas is stopped, and FeCl2 gas is fed instead to grow a semi-insulating current blocking layer 14 made of Fe-doped InP with a thickness of 3 m as shown in FIG. 1 (Ib). The process was carried out. Subsequently, as a second step, a mesa-shaped current carrying portion consisting of a second p-type InP cladding layer was formed. That is, as shown in FIG. 1 (II), instead of removing the mask pattern 13, a dielectric insulating film 16 pattern made of SiO2 is provided, and about 2×10
A second p-type InP cladding layer doped with 18 cm-3 was grown until the top surface of the device was flat. Finally, a semiconductor laser was manufactured through the usual process of providing electrodes 17 and 18 on the front and back screens of the device.

本発明では、従来製法に比べn−成長層が殆どなく、低
量電流値で発振できた。また、活性領域幅も均一で所定
値どおり再現性のよいことが確認された。
In the present invention, there is almost no n-growth layer compared to the conventional manufacturing method, and oscillation can be achieved with a low current value. Furthermore, it was confirmed that the active region width was uniform and had good reproducibility as a predetermined value.

本実施例では第1のp形りラッド層と第2のp形りラッ
ド層が同一のドーピングで同一組成の場合について述べ
たが、必ずしも同一のドーピングや同一組成に限られる
ものではない。
In this embodiment, a case has been described in which the first p-type rad layer and the second p-type rad layer have the same doping and the same composition, but they are not necessarily limited to the same doping or the same composition.

また本実施例ではVPE法を用いたが、有機金属気相成
長法(MOCVD)やガスソース分子ビーム成長法など
を用いても構わない。
Furthermore, although the VPE method is used in this embodiment, metal organic chemical vapor deposition (MOCVD), gas source molecular beam growth, or the like may also be used.

(発明の効果) 本発明によれば、活性層を大気中に露出させずに工程が
行なえ、また活性層領域脇にn−成長層が形成されない
ので従来製造方法に比べもれ電流が少なく高速で動作し
、かつ活性領域幅の制御の容易な半導体レーザを製造で
きる。
(Effects of the Invention) According to the present invention, the process can be performed without exposing the active layer to the atmosphere, and since no n-growth layer is formed next to the active layer region, the leakage current is smaller and the manufacturing speed is faster than in the conventional manufacturing method. Accordingly, it is possible to manufacture a semiconductor laser that operates at a high temperature and whose active region width can be easily controlled.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体レーザの製造方法の工程概略図
、第2図は従来の半導体レーザの製造方法の工程概略図
である。 10・・・n形半導体クラッド層、11・・・活性層、
12・・・第1のp形半導体クラッド層、13・・・マ
スクパターン、14・・・半絶縁性電流阻止層、15・
・・第2のp形半導体クラッド層、16・・・誘電体絶
縁膜、17.18・・・電極、21・・・n−成長層
FIG. 1 is a schematic process diagram of a semiconductor laser manufacturing method according to the present invention, and FIG. 2 is a process schematic diagram of a conventional semiconductor laser manufacturing method. 10... n-type semiconductor cladding layer, 11... active layer,
12... First p-type semiconductor cladding layer, 13... Mask pattern, 14... Semi-insulating current blocking layer, 15...
...Second p-type semiconductor cladding layer, 16...Dielectric insulating film, 17.18...Electrode, 21...N- growth layer

Claims (1)

【特許請求の範囲】[Claims]  活性層が下側をn形半導体クラッド層、上側を第1の
p形半導体クラッド層で挟まれ、活性層の両脇が半絶縁
性電流阻止層により埋込まれた構造を持つ半導体レーザ
の製造方法において第1のp形半導体クラッド層の上に
ストライプ状のマスクパターンを設け、前記マスクパタ
ーン直下の前記活性層まで、実験室中(insitu)
エッチングを行なった後直ちにエッチング溝内及び溝上
に半絶縁性電流阻止層を成長する第1の工程と、前記マ
スクパターンを除去した前記第1のp形半導体クラッド
層の上に第2のp形半導体クラッド層を選択成長しメサ
状電流通電部を形成する第2の工程からなることを特徴
とする半導体レーザの製造方法。
Manufacturing a semiconductor laser having a structure in which an active layer is sandwiched between an n-type semiconductor cladding layer on the lower side and a first p-type semiconductor cladding layer on the upper side, and both sides of the active layer are buried in semi-insulating current blocking layers. In the method, a striped mask pattern is provided on a first p-type semiconductor cladding layer, and the active layer directly under the mask pattern is in situ.
A first step of growing a semi-insulating current blocking layer in and on the etched groove immediately after etching, and a second step of growing a semi-insulating current blocking layer on the first p-type semiconductor cladding layer from which the mask pattern has been removed. 1. A method of manufacturing a semiconductor laser, comprising a second step of selectively growing a semiconductor cladding layer to form a mesa-shaped current carrying part.
JP14879988A 1988-06-15 1988-06-15 Generation of semiconductor laser Pending JPH01316985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14879988A JPH01316985A (en) 1988-06-15 1988-06-15 Generation of semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14879988A JPH01316985A (en) 1988-06-15 1988-06-15 Generation of semiconductor laser

Publications (1)

Publication Number Publication Date
JPH01316985A true JPH01316985A (en) 1989-12-21

Family

ID=15460966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14879988A Pending JPH01316985A (en) 1988-06-15 1988-06-15 Generation of semiconductor laser

Country Status (1)

Country Link
JP (1) JPH01316985A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613711A (en) * 1992-03-25 1994-01-21 American Teleph & Telegr Co <Att> Surface light emitting laser and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613711A (en) * 1992-03-25 1994-01-21 American Teleph & Telegr Co <Att> Surface light emitting laser and manufacture thereof

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