JPH01315161A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize high integration and to reduce a junction capacitance in a device region to a limit by a method wherein a groove for device isolation of a semiconductor integrated circuit and a selective oxide film are formed in a self-aligned manner. CONSTITUTION:A U-shaped groove 2 for device isolation use is formed in a prescribed position in a silicon substrate 1; a silicon oxide film 3, a silicon nitride film 4 and a silicon oxide film 5 are deposited; a sputter etching operation and a side etching operation are executed in edge parts at the upper part of the U-shaped groove 2; the silicon oxide film 3 is exposed. Then, a thermal oxidation operation is executed by making use of the silicon nitride film 4 as a mask; a silicon oxide film 6 for device isolation use is grown selectively on the exposed oxide film 3; the U-shaped groove 2 is blocked; the inside of the U-shaped groove 2 is made hollow. By this setup, it is possible to reduce a device isolation region which is used both as the groove and the selective oxide film, to relax a stress of the semiconductor substrate around the groove, to realize the high integration of a semiconductor integrated circuit and to reduce a junction capacitance in a device region.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region of a semiconductor integrated circuit that uses a trench for isolation and a selective oxide film. In order to increase the integration density of a semiconductor integrated circuit and to reduce the junction capacitance in the conductor region, a step of forming a groove for element isolation on a semiconductor substrate, and a step of forming a groove on the semiconductor substrate on the radiator side. a step of sequentially forming a non-oxidizing film and a mask film; a step of selectively etching the mask film at an edge portion above the groove to expose the non-oxidizing film; and a step of exposing the non-oxidizing film. and a step of selectively oxidizing an oxide film for element isolation at the edge portion of the upper part of the trench using the side-etched non-oxidizing film as a mask.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an isolation region of a semiconductor integrated circuit using a trench for isolation and a selective oxide film.

In recent years, as semiconductor integrated circuits have become faster and more highly integrated, thick oxide films have been formed on elements to reduce capacitance between element wirings, and oxide films have been formed on semiconductor substrates to reduce element isolation regions. It is required to perform element isolation using a high-temperature method.

Device isolation using this oxide film is usually used in combination with device isolation using an oxide film selectively formed on a semiconductor substrate.

Furthermore, even in device isolation methods using these methods in combination with a selective oxide film, there is a need to further reduce the size of the device isolation region.

[Prior Art] In a conventional method for forming an element isolation region of a semiconductor integrated circuit using a combination of an element isolation method and a selective oxide film, lithography technology is used to align the trench and the selective oxide film. .

That is, as shown in FIG. 3, a silicon oxide film 1 having a width A is formed on a silicon substrate 11 as a semiconductor substrate.
2 is selectively formed, and the silicon substrate 11 is etched through an opening with a width B made in this silicon oxide film 12 using lithography technology.
A U eraser 13 having a width B is formed on top. In order to always position the U groove 13 having a width B inside the width A of the silicon oxide M12, a mask with a width A and a %SB
A margin of alignment with the mask was required.

As the device area is reduced by establishing a method for forming a self-aligned junction, this alignment margin can no longer be ignored. For this reason, we are trying to reduce the alignment margin using advanced phosphorography equipment, but it is impossible to completely eliminate it in principle, and it is still 0.1
There is an alignment margin of μm to 0.2 μm. Therefore, even when reducing the device surface precision, this alignment margin must be taken into account, which impedes the high integration of semiconductor integrated circuits and causes the problem that the junction capacitance in the device region cannot be reduced to the maximum. was occurring.

In addition, in the conventional method of forming an element isolation region of a semiconductor integrated circuit using an element isolation groove, as shown in FIG. A layer 15 is deposited, and the upper surface of the polycrystalline silicon layer 15 is cap oxidized to form a silicon oxide WA 16.
Element isolation is carried out in the same way as adding pure sauce. However, when cap oxidizing the upper surface of the polycrystalline silicon layer 15, the silicon acid 1 arsenic film 1 due to the cap oxidation
Due to the volumetric expansion accompanying the formation of 6, a large stress is generated in the semiconductor substrate 11 around the groove shown at part 0 in FIG. 4, and crystal defects are formed. When an element is formed on the surface of a semiconductor substrate having such crystal defects, a problem arises in that leakage current is generated along the crystal defects, for example, their dislocations, leading to deterioration of the characteristics of the element.

[Problems to be Solved by the Invention] As described above, according to the above-mentioned conventional method, since a margin for alignment between the element isolation groove and the selective oxide film is required, reduction of the element area is hindered, and therefore the semiconductor This has hindered the high integration of integrated circuits and has caused the problem that the junction capacitance in the element region cannot be reduced to the utmost limit.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the element isolation region to increase the integration density of a semiconductor integrated circuit and to reduce the junction capacitance in the element region.

In addition, in the conventional method, when cap oxidizing the upper surface of the polycrystalline silicon layer deposited in the groove for separating the cables, large stress is generated in the semiconductor substrate around the groove, leading to deterioration of device characteristics. A problem had arisen.

Therefore, an object of the present invention is to alleviate the stress on the semiconductor substrate around the trench and improve device characteristics.

Means for Solving the Problem] The above problem consists of a step of forming a trench for element isolation on a semiconductor substrate, and a step of sequentially forming a non-oxidizing film and a mask film on the semiconductor substrate inside the trench. , a step of selectively etching the mask film at an edge portion above the groove to expose the non-oxidizing film; a step of side-etching the exposed non-oxidizing film; and a step of etching the side-etched non-oxidizing film. This is achieved by a method of manufacturing a semiconductor device, comprising the step of selectively oxidizing an oxide film for element isolation at the edge portion of the upper part of the groove using an oxidizing film as a mask.

Further, the above problem is solved by 'fI!' of a semiconductor device characterized in that the groove is closed by the oxide film. This is achieved through the method of communication.

Alternatively, the above-mentioned object is achieved by a method for manufacturing a semiconductor device, characterized in that after forming the oxide film, a filler is buried in the trench, and an insulating film is formed on the filler.

[Function] That is, the present invention forms an oxide film selectively formed above the trench for element isolation in a self-aligned manner with the trench.

This reduces the element isolation region in which the trench and selective oxide film are used together.

Further, in the present invention, the trench is closed by a selective oxide film formed in self-alignment with the trench for element isolation, thereby making the inside of the trench hollow. This relieves stress on the semiconductor substrate around the trench.

Alternatively, in the present invention, after a selective oxide film is formed in a self-aligned manner above a trench for element isolation, a filling material is deposited in the trench, and an insulating film is formed on the filling material. This relieves stress on the semiconductor substrate around the trench.

[Example 1] Hereinafter, the present invention will be specifically described based on an illustrative example.

FIG. 1 is a process diagram showing a method for forming an element isolation region of a semiconductor integrated circuit according to a first embodiment of the present invention, and FIG. 2 is a process diagram showing the formation of an element isolation region of a semiconductor integrated circuit according to a second embodiment of the present invention. It is a process chart showing a method.

At a predetermined position on a silicon substrate 1 as a semiconductor substrate,
For example, using chlorine-based reactive ion etching (RIB), a U-shaped groove 2, for example, having a U-shape for element isolation and having a width of 1.0 um or less and a depth of about 5.0 .mu.m is formed. Subsequently, the surface of the silicon substrate 1 including the inner surface of this U-groove 2 is thermally oxidized to form a silicon oxide film 3 with a thickness of about 1000 Å.

Furthermore, a non-oxidizing film such as silicon nitride M4 as an insulating film that does not oxidize even in an oxygen atmosphere is deposited on the silicon oxide M3 with a thickness of approximately 1000 nm by chemical vapor deposition (CVD), and then this silicon nitride film Deposit about 1,000 silicon oxide M5 as a mask film on 4 using the same CVD method (Fig. 1(a)).
. Note that the silicon oxide film 3 is formed to relieve stress caused by the formation of the silicon nitride WA4.

Next, by sputter etching, the silicon oxide film 5 at the edge portion above the U-groove 2 is etched away, and a portion of the silicon nitride M4 is exposed. Note that the etching of this edge portion is carried out under conditions such that the etching speed of sputter etching is maximum at a corner having an angle of 45° (FIG. 1(b)).

Next, using hot phosphoric acid at a temperature of 160°C to 170°C,
Side etching of the silicon nitride M4 is performed in the horizontal and vertical directions from the exposed portion of the edge portion to expose the silicon oxide film 3. The side etching of the silicon nitride film 4 at this time is approximately 5 μm in both the horizontal and vertical directions from the edge portion (FIG. 1(C)).

Next, thermal oxidation is performed using the silicon nitride WA4 as a mask, and a silicon oxide film 6 for element isolation is selectively grown on the exposed silicon oxide film 3 at the edge portion of the U well 2. At this time, by growing the silicon oxide M6 to a thickness of approximately 1 μm or more, the silicon oxide film 6 that grows from the edge portions on both sides of the upper part of the U-container 2 closes the U-container 2, making the inside of the U-container 2 hollow ( Figure 1 (d)).

Next, the silicon oxide 11i5 and the silicon nitride WA4 above the silicon substrate 1 except for the inside of the U-groove 2 are removed by etching. However, during this etching, etching conditions are set so that the silicon oxide M6 blocking the U-groove 2 does not open again (FIG. 1(e)).

In this way, a silicon oxide FIA 6 is formed on the edge of the upper part of the U film 2 for element isolation in a self-aligned manner with the U film 2, and the silicon oxide film 6 blocks the U film 2.
Make the inside of U-ko 2 hollow.

According to the first embodiment, the silicon oxide WA6 is formed in a self-aligned manner with the U-groove 2 in order to serve as a mask when side-etching the silicon nitride film 4 to form the silicon oxide WA6. I can do it. Therefore, the alignment margin between the U-groove 2 and the silicon oxide film 6, which are also used for element isolation, can be omitted, and the element isolation region can be reduced. Therefore, the semiconductor integrated circuit can be highly integrated, and the junction capacitance in the element region can be reduced to the utmost as the element area is reduced. Further, by making the inside of the U groove 2 hollow, stress on the silicon substrate 1 around the U groove 2 can be significantly alleviated.

Therefore, element characteristics can also be improved.

Note that in the first embodiment, the silicon nitride film 4
After exposing the silicon oxide film 3 by side etching, the silicon oxide film 6 is selectively grown by thermal oxidation, and then the silicon oxide film 5 and silicon nitride 14 above the silicon substrate 1 except for the inside of the U well 2 are grown. The silicon oxide film 5 is removed by etching after the silicon oxide rfA 3 is exposed by side etching the silicon nitride film 4, and then the silicon oxide film 6 is selectively grown by thermal oxidation. , followed by U
Silicon nitride JI above the silicon substrate 1 excluding the inside of the silicon 2
I4 may be removed by etching.

In this case, when removing the silicon oxide WA5 by etching, the exposed silicon oxide M3 is also etched, but this does not affect the selective growth of the silicon oxide Jli6 by subsequent thermal oxidation. Furthermore, in the insulating layer formed on the silicon substrate 1 inside the U well 2, the silicon oxide M5 is removed and finally the silicon oxide W
Although it is composed of A3 and silicon nitride 11!4, it does not affect the element isolation effect.

Next, a second embodiment of the present invention will be described using FIG. 2.

The steps shown in FIGS. 2(a) to (c) are exactly the same as the steps shown in FIGS. 1(a) to (C) in the first embodiment. Through these steps, a U-groove 2 for element isolation is formed on the silicon substrate 1, a silicon oxide film 3, a silicon nitride film 4, and a silicon oxide film 5 are sequentially deposited, and then the upper edge of the U-groove 2 is etched by sputter etching. The silicon oxide film 5 in the area is removed by etching, and then the exposed silicon nitride film 4 is side-etched.

Next, thermal oxidation is performed using the silicon nitride film 4 as a mask, and a silicon oxide film 6 for element isolation is selectively grown on the exposed silicon oxide M3 at the edge portion of the substrate 2.
At this time, the silicon oxide film 6 is grown to a thickness of about 0.5 μm, for example, so that the silicon oxide film 6 grown from the edge portions on both sides of the upper part of the U groove 2 is not connected, and the U groove 2 remains open. Keep it.

Next, after depositing a polycrystalline silicon layer 7 over the entire surface, the polycrystalline silicon layer 7 is etched from above, leaving the polycrystalline silicon layer 7 as a filler only in the bowl 2. Subsequently, the exposed surface of the polycrystalline silicon layer 7 in Ufi2 is cap oxidized to form silicon oxide WA8 on this polycrystalline silicon layer 7. And this silicon oxide film 8
is connected to the silicon oxide 16 selectively formed on the edge portion of the U groove 2, forming a structure in which the polycrystalline silicon layer 7 embedded in the U groove 2 is colored (Fig. 2(d)). ).

Next, the silicon oxide WA 5 and the silicon nitride film 4 above the silicon substrate 1 except for the inside of the U-tube 2 are removed by etching (see FIG. 2(e)).

In this way, silicon oxide 11i3, silicon nitride wA4, and silicon oxide 11i6 are formed in the upper edge of U-groove 2 for element isolation in a self-aligned manner with this U-groove 2. A polycrystalline silicon layer 7 serving as a filler is buried through an oxide film 5, and the surface of the buried polycrystalline silicon layer 7 is cap oxidized to form a silicon oxide layer 1.
]18 to close the lid.

In this case, the cap oxidation time is only the time required to insulate the surface of the polycrystalline silicon layer 7 because the silicon oxide film 6 has already been formed on the edge portion of the U-layer 2, and is therefore shorter than in the conventional case. .

In this way, in the second embodiment, as in the first embodiment, the silicon oxide film 6 is formed in a self-aligned manner with respect to the U trench 2. It is possible to reduce the size of the element isolation region made up of the silicon oxide film 2 and the silicon oxide film 6.

Furthermore, when cap oxidizing the upper surface of the polycrystalline silicon layer 7 embedded in the U-groove 2, stress is generated in the silicon substrate 1 around the U-groove 2 due to the cap oxidation, but the oxidation time is longer than that of the conventional cap. The time required for oxidation may be shorter, and therefore the stress generated is greatly reduced. Therefore, it is possible to improve the deterioration of the characteristics of the element due to the stress generation.

Note that in the second embodiment, the silicon nitride film 4
After exposing the silicon oxide film 3 by side etching, a silicon oxide film 6 is selectively grown, a polycrystalline silicon layer 7 is deposited in the U-groove 2, and silicon oxidation is performed on this polycrystalline silicon layer 7. The film 8 is sequentially formed, and then the silicon oxide WA5 and the silicon nitride WA4 above the silicon substrate 1 except for the inside of the U-groove 2 are sequentially etched away. After exposure, silicon oxide IA
After that, a silicon oxide film 6 is selectively grown by thermal oxidation, a polycrystalline silicon layer 7 is deposited in the trench 2, and a silicon oxide film 8 is deposited on the polycrystalline silicon layer 7. Formation is carried out sequentially, followed by U clearing 2.
Silicon nitride l above the silicon substrate 1 excluding the inside! li
4 may be removed by etching.

Further, in the second embodiment, the polycrystalline silicon layer 7 is embedded in the cavity 2, but it is not limited to the polycrystalline silicon layer 7, and may be a mixture of polycrystalline silicon and polycrystalline germanium, etc. Good too.

When a mixture of polycrystalline silicon and polycrystalline germanium is embedded as a filler, oxidizing the upper surface of the filler evaporates the germanium in the filler, thereby controlling the volumetric expansion of the oxide film formed by cap oxidation. , it is possible to reduce the stress generated in the silicon substrate 1 around the U-layer 2.

[Effects of the Invention] As described above, according to the present invention, the grooves and the selective oxide film are formed in a self-aligned manner to isolate the elements of a semiconductor integrated circuit, so that the grooves and the selective oxide film are used together. It is possible to reduce the element isolation region, thereby achieving higher integration of the semiconductor integrated circuit, and also to improve the performance of the semiconductor integrated circuit by reducing the junction capacitance in the element region to the utmost limit.

Further, according to the present invention, by closing the trench with a selective oxide film formed in self-alignment with the trench for element isolation and making the trench hollow, the stress on the semiconductor substrate around the trench is significantly alleviated. It is possible to improve device characteristics.

Alternatively, according to the present invention, after forming a selective oxide film in a self-aligned manner above the trench for element isolation, a filling material is embedded in the trench, and an insulating film is formed on the filling material, thereby forming a film around the trench. The stress on the semiconductor substrate can be alleviated, and device characteristics can therefore be improved.

[Brief explanation of the drawing]

1 is a process diagram showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention; FIG. 2 is a process diagram showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention; FIG. FIG. 4 is a cross-sectional view showing problems of conventional semiconductor device manufacturing methods. In the figure, 1... Semiconductor substrate (silicon substrate) 2...
...Whole (U groove) for element isolation 3...Silicon oxide film by thermal oxidation 4...Non-oxidizing g (CVD
Silicon oxidation 5...Mask film (CVD)
silicon oxide film) 6...Oxide film for element isolation (silicon substrate) 7...Filling material (polycrystalline silicon layer) 8...Insulating film (silicon oxide film) ).

Claims (1)

[Claims] 1. A step of forming a groove (2) for element isolation on a semiconductor substrate (1), and forming a non-oxidizing film (4) on the semiconductor substrate (1) inside the groove (2). ) and a mask film (5), and selectively etching the mask film (5) at the upper edge of the groove (2) to expose the non-oxidizing film (4). , a step of side-etching the exposed non-oxidizing film (4), and using the side-etched non-oxidizing film (4) as a mask, forming an oxide film for element isolation on the edge portion of the upper part of the groove (2). (6) A method for manufacturing a semiconductor device, comprising the step of selectively oxidizing. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the trench (2) is closed by the oxide film (6). 3. In the method according to claim 1, after forming the oxide film (6), a filler (7) is embedded in the groove (2), and an insulating film (8) is formed on the filler (7). 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.