JPH01309357A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01309357A JPH01309357A JP63141055A JP14105588A JPH01309357A JP H01309357 A JPH01309357 A JP H01309357A JP 63141055 A JP63141055 A JP 63141055A JP 14105588 A JP14105588 A JP 14105588A JP H01309357 A JPH01309357 A JP H01309357A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- stress
- semiconductor chip
- mold resin
- assembly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000011347 resin Substances 0.000 claims abstract description 53
- 229920005989 resin Polymers 0.000 claims abstract description 53
- 238000000465 moulding Methods 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000012467 final product Substances 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract 2
- 230000035882 stress Effects 0.000 description 18
- 238000000034 method Methods 0.000 description 12
- 239000004642 Polyimide Substances 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 238000007789 sealing Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920005575 poly(amic acid) Polymers 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
この発明は半導体装置の樹脂封止構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin sealing structure for a semiconductor device.
〔従来の技術］
第２図は従来の樹脂対土工程の半導体装置の断面図を示
す。[Prior Art] FIG. 2 shows a cross-sectional view of a semiconductor device in a conventional resin-to-soil process.
図において、α）は半導体ｔラグ、伐）は半導体チツ１
α）をダイボンドするフレーム、（３）はリード、（４
）は半導体チップα）上のボンディングパッド（図示せ
ず）と上記リード（３）とを電気的に接続するボンディ
ングワイヤ、（７）はモールド樹月旨である。In the figure, α) is the semiconductor t-lag, and
α) is the frame to be die-bonded, (3) is the lead, (4
) is a bonding wire that electrically connects the bonding pad (not shown) on the semiconductor chip α) and the lead (3), and (7) is a molding wire.
次に、組立て封止工程に従って従来の組み立て封止構造
を説明する。半導体装置をウェハ上に形成後、ダイリン
グして個々の半導体チップ（１）に分離する０この半導
体チップ（１）を第２図０）に示すように、フレーム（
２）上に半田、樹脂等によシダイボンドし、半導体チッ
プα）上のボンティングパッドとリード（３）とをワイ
ヤボンディングして接続する。このボンディングワイヤ
（４）には金、アルミニウム（又はその合金）、銅（又
はその合金）等が用いられる。Next, a conventional assembly and sealing structure will be explained according to the assembly and sealing process. After semiconductor devices are formed on a wafer, the semiconductor chips (1) are separated into individual semiconductor chips (1) by die-ring.As shown in FIG.
2) Die bonding is performed using solder, resin, etc. on the semiconductor chip α), and the bonding pads on the semiconductor chip α) and the leads (3) are connected by wire bonding. Gold, aluminum (or its alloy), copper (or its alloy), etc. are used for this bonding wire (4).
このリードフレームに固定された半導体チップα）を金
型に入れモールド樹脂（′７）を注入して封止する（第
２図（ｂ））。The semiconductor chip α) fixed to this lead frame is placed in a mold and molded resin ('7) is injected to seal it (FIG. 2(b)).
この後、リード（３）を個々のパッケージ毎に切シ離し
、リード（３）を曲げて樹脂封止半導体装置ができ上が
る（第２図（Ｃ））。Thereafter, the leads (3) are cut into individual packages, and the leads (3) are bent to complete a resin-sealed semiconductor device (FIG. 2(C)).
このモールド樹脂（７）としては通常エポキン系の樹脂
が用いられ、半導体チップ（１）と熱膨張係数が近くな
るように、アμミナ等の微粒子（フィツーと呼ばれる）
を混合することが多い。そして、モールド樹脂（７）Ｋ
は外部からの水分、不純物等の侵入を防止し、デバイス
を安定に動作させることのできる性能が求められる。Epoquin resin is usually used as the molding resin (7), and fine particles such as amiumina (called fitwo) are used so that the coefficient of thermal expansion is close to that of the semiconductor chip (1).
are often mixed. And mold resin (7) K
Devices are required to have performance that prevents the intrusion of moisture, impurities, etc. from the outside and allows devices to operate stably.
ところが、近年デバイス構造が微細化されるのに従って
、半導体ｔツブ（１）がモールド樹脂（７）から受ける
応力によるリーク、メモリ揮発、誤動作等の不良が顕在
化し、七−ルド樹脂（７）に対して低応力化の要求が強
い。However, as device structures have become finer in recent years, defects such as leaks, memory volatilization, and malfunctions due to the stress that the semiconductor T-tube (1) receives from the mold resin (7) have become apparent. In contrast, there is a strong demand for lower stress.
この不良はモールド樹脂中のフィツーによる局所的な応
力が原因となっていることも多い。このような応力を緩
和する手段としては従来、モールド樹脂（７）を低応力
化することが行なわれてき九が、謝湿性等の性能を保ち
つつ低応力化するのは制限があった。This defect is often caused by localized stress caused by fitwo in the mold resin. Conventionally, as a means of alleviating such stress, reducing the stress of the mold resin (7) has been carried out.However, there are limitations in reducing the stress while maintaining performance such as moisture resistance.
そこで、特に、このような応力に敏感なデバイスではポ
リイミド等によるバッファコート膜（ストレスＭ衝膜）
をチップ表面に形成して、モールド樹脂（７）と半導体
チップ（１）とが直接、接さないようにしている。Therefore, especially for such stress-sensitive devices, a buffer coat film (stress M film) made of polyimide etc. is used.
is formed on the chip surface to prevent direct contact between the mold resin (7) and the semiconductor chip (1).
モールド樹脂（７）の曲げ弾性率が１０００射／−以上
と大きいのに対し、ポリイミドでは約３００４ｆ／−と
小さく半導体チップ（１）にかかる応力は大きく緩和さ
れるＱ
バッファコート膜形成には通常スピンコード法又はボッ
ティング法が使われる。The bending elastic modulus of the mold resin (7) is large at over 1000 f/-, whereas polyimide has a small modulus of about 3004 f/-, which greatly alleviates the stress applied to the semiconductor chip (1). A spin code method or a botting method is used.
スピンコード法は半導体装置を個々のチップに分離する
以前に、ウェハ状態で液状のポリイミド前駆体（ポリア
ミック酸溶液）等を回転塗布し、その上に更にレジスト
を塗布し、露光・現像して、ボンディングパッド部等不
用の部分のポリイミドをエラをラグ除去した後、レジス
トを剥離することでバターニング後、加熱し硬化させる
ことでバッファコートを形成する感光性ポリイミドでは
レジスト塗布・現像剥離が省略できる。In the spin code method, before a semiconductor device is separated into individual chips, a liquid polyimide precursor (polyamic acid solution) is spin-coated on the wafer, a resist is further coated on top of the coating, and then exposed and developed. After removing the lag from the polyimide in unnecessary areas such as bonding pads, the resist is peeled off. After buttering, a buffer coat is formed by heating and curing. With photosensitive polyimide, resist application and development peeling can be omitted. .
ポツティング法では半導体チップＵ＞をフＶ−ム上にダ
イボンドし、ワイヤボンディング迄完了した状態で液状
のポリイミド前駆体（ポリアミック酸溶液）等を滴下し
、チップ表面を被うようにして、加熱し、硬化させパッ
クアコートとする。In the potting method, a semiconductor chip U is die-bonded onto a frame, and after wire bonding is completed, a liquid polyimide precursor (polyamic acid solution) is dropped to cover the chip surface and heated. , cured and made into packacoat.
但し、ボッティング法では１ｆツグづつ滴下していくこ
とが必要な上、バッファコート膜と、モールド樹脂（７
）との界面でせん断応力が発生し、ボンダイングワイヤ
（４）を切断するという不良が発生することがあった（
第３図参照）。However, in the botting method, it is necessary to drop 1 f drop at a time, and the buffer coat film and mold resin (7
) Shear stress was generated at the interface with the bonding wire (4), resulting in a defect where the bonding wire (4) was cut (
(See Figure 3).
スピンコード法ではこのような不良は発生しないが、工
程が長く材料・加工コストが高い。Although such defects do not occur with the spin cord method, the process is long and material and processing costs are high.
〔発明が解決しようとする課題Ｊ
従来の半導体装置は以上のように構成されていたので、
モールド樹脂の応力によシ誤動作した夛、メモリデバイ
スでは配憶内容が揮発するなどの問題点かあシ、又、バ
ッファコート材を用いる方法では工程が長くなシ、工期
やコスト面で大きな不利があった〇
この発明は上記のような問題点を解消するためになされ
たもので、安価で容易に附湿性を損うことなくモールド
樹脂の応力を低減し、この応力による不良の発生を抑え
ることのできる半導体装置を得ることを目的とする。[Problem to be solved by the invention J Since the conventional semiconductor device was configured as described above,
There are problems such as malfunctions caused by stress in the mold resin, and memory contents volatilize in memory devices.Also, methods using buffer coat materials require a long process, which is a big disadvantage in terms of construction time and cost. 〇This invention was made to solve the above problems, and it is an inexpensive and easy method to reduce the stress in the molding resin without impairing moisture content, thereby suppressing the occurrence of defects due to this stress. The purpose is to obtain a semiconductor device that can perform
〔！Ｉ題を解決するための手段Ｊ
この発明の半導体装置はフレームと半導体ｔラグとボン
ダイングワイヤおよびリード基部を内包する第１のモー
ルド樹脂と、この第１のモールド樹脂を更に１＠シ大き
く内包する第２のモールド樹脂とによつ 構成されるも
のである。[! Means for Solving Problem I J The semiconductor device of the present invention includes a first mold resin that includes a frame, a semiconductor T-lug, a bonding wire, and a lead base, and a larger size of the first mold resin. and a second mold resin.
［作用ｊ
この発明における半導体装置は第２のモールド樹脂によ
ル外部からの水分、不純物等の侵入を抑え、大きな機械
的強度を得るとともに第１のモールド樹脂によシ上紀第
２のモールド樹脂によって発生する機械的応力を吸収し
半導体チップＫかかる応力を抑える。[Function j] The semiconductor device of the present invention uses the second molding resin to suppress moisture, impurities, etc. from entering the mold from the outside, and obtains great mechanical strength, and the semiconductor device uses the first molding resin to suppress the intrusion of moisture, impurities, etc. from the outside. It absorbs the mechanical stress generated by the resin and suppresses the stress applied to the semiconductor chip K.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、（１）は半導体チップ、（２）はフレ
−五、（３）はリード、（４）はボンディングワイヤ、
（５）は第１の七−μド樹脂、（６）は第２のモールド
ｗ脂である。In Figure 1, (1) is a semiconductor chip, (2) is a frame, (3) is a lead, (4) is a bonding wire,
(5) is the first 7-μ resin, and (6) is the second mold resin.
第１図（ａ）に示した様に、従来例に示したのと同様に
半導体チップα）ｔフレーム（２）上にダイボンドし、
リード（３）とポンチ゛イングパツドをワイヤボンディ
ングによシ接続する。As shown in FIG. 1(a), the semiconductor chip α) is die-bonded onto the T-frame (2) in the same way as shown in the conventional example,
Connect the lead (3) and punching pad by wire bonding.
これを第１の最終品よシ小さな金型に入れ樹脂を注入し
て、第１のモールド樹脂（５）中に封止する（第１図（
ｂ））。This is placed in a mold smaller than the first final product, injected with resin, and sealed in the first mold resin (5) (see Figure 1).
b)).
次に、第２の金型に入れ、同じように樹脂を注入して第
２のモールド樹脂（６）中に封止し、リードを曲げて最
終品とする（第１図（Ｃ））。Next, it is placed in a second mold, and resin is injected in the same manner to seal it in the second mold resin (6), and the leads are bent to form a final product (FIG. 1(C)).
ここで、第２のモールド樹脂（６）は機械的強度に優れ
、密封性の高い従来通夛のエボキＶ系樹脂（セラミック
魚粒子などのフィツーを混入したものを含む）を用いれ
ば良い。この際特に樹脂のストレス等を考慮する必要は
ない。Here, the second molding resin (6) may be a conventional EBOKI V-based resin (including one mixed with FITSU such as ceramic fish particles) which has excellent mechanical strength and high sealing performance. At this time, there is no need to take into account the stress of the resin.
そして、第１０モーμド樹脂（５）は上紀第２のモール
ド樹脂（６）が半導体チップ（１）に与える応力を緩和
するように、曲げ弾性率の小さい、柔かい樹脂を用いる
。As the 10th mode μ mode resin (5), a soft resin having a small bending elastic modulus is used so as to relieve the stress exerted on the semiconductor chip (1) by the second molding resin (6).
このとき、熱ストレスによシ第２のモールド樹脂（２）
にクラックが入ることを防ぐために、半導体チップα〕
（フレーム（２） ） 、第１のモールド樹脂（５）・
第２のモールド樹脂（６）の熱膨張係数がほぼ同程度に
なっていることが望ましい。At this time, to prevent heat stress, the second mold resin (2)
To prevent cracks from forming on the semiconductor chip α]
(Frame (2)), first mold resin (5)
It is desirable that the coefficients of thermal expansion of the second mold resin (6) are approximately the same.
尚、上記実施例では第１のモールド樹脂と第２のモール
ド樹脂よシなる２層構造のモールドパッケージについて
説明したが、必要であれば更に層を増した多層構造とし
てもよい０
〔発明の効果Ｊ
以上の様にこの発明によれば２層のモールド樹脂を用い
たので優れた機械的強度、耐湿性ならびに半導体チップ
に対する低応力とを両立し得る効果がある。Incidentally, in the above embodiment, a mold package having a two-layer structure consisting of a first mold resin and a second mold resin was explained, but if necessary, a multi-layer structure with further layers may be used. J As described above, according to the present invention, since a two-layer molding resin is used, it is possible to achieve both excellent mechanical strength, moisture resistance, and low stress on the semiconductor chip.
第１図（ａ）〜（ｅ）はこの発明の一実施例による半導
体装置の製造工程を示す断面図、第２図仏〕〜（Ｃ）は
従来の半導体装置の製造工程を示す断面図、第３１文は
従来のボッティングによるパックアコートを採用した半
導体装置を示す部分拡大断面図である０図において、α
）は半導体チップ、Ｃ２）はフレーム、（３）はリード
、（４）はボンディングワイヤ、（５）ｔ （６）は第
１および第２のモールド樹脂を示す。
尚、図中、同一符号は同一、又は相当部分を示すＯ
代 理 人 大 岩 増 進第１図
（ａ＞ 第２図
（Ｃ）
第３図1(a) to (e) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to (C) are cross-sectional views showing the manufacturing process of a conventional semiconductor device, The 31st sentence is α
) is a semiconductor chip, C2) is a frame, (3) is a lead, (4) is a bonding wire, (5) t (6) is a first and second mold resin. In addition, the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
半導体チップ上のボンディングパッドとリードとを電気
的に接続するボンディングワイヤと上記フレーム、半導
体チップ、ボンディングワイヤ、及びリード基部とを内
包するようにして形成された第１のモールド樹脂と、こ
の第１のモールド樹脂を内包するような更に１回り大き
な第２のモールド樹脂とからなることを特徴とする半導
体装置。The semiconductor chip die-bonded on the frame, the bonding wire that electrically connects the bonding pads on the semiconductor chip and the leads, and the frame, the semiconductor chip, the bonding wire, and the lead base are formed so as to enclose them. 1. A semiconductor device comprising: a first mold resin that is larger than the first mold resin; and a second mold resin that is one size larger and encloses the first mold resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63141055A JPH01309357A (en) | 1988-06-07 | 1988-06-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63141055A JPH01309357A (en) | 1988-06-07 | 1988-06-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01309357A true JPH01309357A (en) | 1989-12-13 |
Family
ID=15283206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63141055A Pending JPH01309357A (en) | 1988-06-07 | 1988-06-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01309357A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7425470B2 (en) * | 2003-03-04 | 2008-09-16 | Micron Technology, Inc. | Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths |
-
1988
- 1988-06-07 JP JP63141055A patent/JPH01309357A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7425470B2 (en) * | 2003-03-04 | 2008-09-16 | Micron Technology, Inc. | Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths |
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