JPH01309343A - Mounting of semiconductor device - Google Patents
Mounting of semiconductor deviceInfo
- Publication number
- JPH01309343A JPH01309343A JP63140868A JP14086888A JPH01309343A JP H01309343 A JPH01309343 A JP H01309343A JP 63140868 A JP63140868 A JP 63140868A JP 14086888 A JP14086888 A JP 14086888A JP H01309343 A JPH01309343 A JP H01309343A
- Authority
- JP
- Japan
- Prior art keywords
- sheet
- substrate
- electrode
- semiconductor chip
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000003466 welding Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910020658 PbSn Inorganic materials 0.000 description 2
- 101150071746 Pbsn gene Proteins 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
- H01L2224/75101—Chamber
- H01L2224/75102—Vacuum chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/79—Apparatus for Tape Automated Bonding [TAB]
- H01L2224/7925—Means for applying energy, e.g. heating means
- H01L2224/793—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/79301—Pressing head
- H01L2224/79314—Auxiliary members on the pressing surface
- H01L2224/79317—Removable auxiliary member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の実装方法、詳しくは半導体装ノ
ブを回路基板の上に実装して相互の電極を接続する技術
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting a semiconductor device, and more particularly to a technique for mounting a semiconductor device knob on a circuit board and connecting mutual electrodes.
（従来の技術〕
第３図は従来の技術による半導体装置を示す断面図であ
り、第４図は第３図のものを生産する工程の一段階を示
す断面図である。(Prior Art) FIG. 3 is a cross-sectional view showing a semiconductor device according to the prior art, and FIG. 4 is a cross-sectional view showing one step in the process of producing the device shown in FIG.
従来、バンプ電極１を持った半導体チップ２を金属層の
基板電極３を持った回路基板４に実装するには、第４図
に示すようにバンプ電極１が基板電極３に当接するよう
Ｑこ置き、半導体チップ２又は基板４の背面に図示しな
い加熱ブロックを当てがって加熱することにより、ハン
プ電極１と基板電極３を融かして一体化する。このよう
にして、第３図に示すように一体化した相互の電極の合
金層５によって電気的に接続された半導体チ・ノブ２と
回路基板４とからなる半導体装置が得られる。Conventionally, in order to mount a semiconductor chip 2 having a bump electrode 1 on a circuit board 4 having a metal layer substrate electrode 3, the bump electrode 1 is placed in contact with the substrate electrode 3 as shown in FIG. A heating block (not shown) is applied to the back surface of the semiconductor chip 2 or the substrate 4 to heat it, thereby melting and integrating the hump electrode 1 and the substrate electrode 3. In this way, as shown in FIG. 3, a semiconductor device consisting of the semiconductor chip 2 and the circuit board 4 electrically connected by the alloy layer 5 of the mutually integrated electrodes is obtained.
ハンプ電極１はＰｂ Ｓｎ系のはんだを盛り上げて形成
され、一方セラミック又はエポキシ樹脂ブロック若しく
はフィルム等からなる基板４の上の基板電極３はＰｂ
Ｓｎ系はんだ又はＮｉ等が金属層として形成されている
。The hump electrode 1 is formed by piling up PbSn-based solder, while the substrate electrode 3 on the substrate 4 made of ceramic or epoxy resin block or film is made of PbSn-based solder.
Sn-based solder, Ni, or the like is formed as a metal layer.
前記の従来の技術ではハンプ電極１と基板電極３との合
金層５を形成するために、２５０〜３５０°Ｃ程度に加
熱する必要がある。この時、半導体チップ２の熱膨張係
数はＳｉの場合２８８〜３．５ｘｌｏ−６／’ｃ、基板
４の熱膨張係数はエポキシ樹脂の場合２８〜３５ Ｘ
１０−’／”Ｃ、セラミックの場合６．５〜１０． ２
Ｘ １０−’／’Ｃであり、この熱膨張係数の差によ
って接続部に歪みや断線が生じることがあるという問題
がある。また加熱温度が高すぎて半導体チップや基板を
損傷することのないように、又は低すぎて電極の接続が
弱くなることのないようにするため加熱温度管理に手間
がかかるという問題もある。In the conventional technique described above, in order to form the alloy layer 5 of the hump electrode 1 and the substrate electrode 3, it is necessary to heat it to about 250 to 350°C. At this time, the thermal expansion coefficient of the semiconductor chip 2 is 288 to 3.5xlo-6/'c in the case of Si, and the thermal expansion coefficient of the substrate 4 is 28 to 35x in the case of epoxy resin.
10-'/”C, 6.5 to 10.2 for ceramic
X 10-'/'C, and there is a problem in that this difference in thermal expansion coefficient may cause distortion or disconnection in the connection portion. Another problem is that it takes time and effort to manage the heating temperature in order to prevent the heating temperature from being too high and damaging the semiconductor chip or the substrate, or too low and weakening the connection between the electrodes.
この発明は半導体チップと回路基板とに熱膨張係数の差
があっても接続部に歪みや断線の問題が生じることがな
い半導体装置の実装方法を得ることを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for mounting a semiconductor device that does not cause problems such as distortion or disconnection in connection parts even if there is a difference in thermal expansion coefficient between a semiconductor chip and a circuit board.
この発明は前記の課題を解決するために、半導体装置の
実装方法に関し、半導体チップと基板とを相互の電極が
当接するように対向させて可撓性のシートで気密に包み
、このシートに設けた吸気口を介して前記シートの内部
を真空にして前記相互の電極を圧接するように構成する
。In order to solve the above-mentioned problems, the present invention relates to a method for mounting a semiconductor device, in which a semiconductor chip and a substrate are faced to each other so that their electrodes are in contact with each other, and are airtightly wrapped in a flexible sheet. The interior of the sheet is evacuated through an air intake port, and the electrodes are brought into pressure contact with each other.
半導体装置の実装方法に関し、シート１１の内外の圧力
差によって半導体チップ２又は基板４の背面の面積のう
ちいずれか一方の狭い面積に前記圧力差を乗じた値の接
触力が相互の電極１と３の間に作用する。半導体チップ
２又は基板４の背面の面積は複数の電極の接触面の全面
積より一般にはるかに大きいので電極相互の接触圧はシ
ート内外の圧力差よりはるかに大きくなる。Regarding the method of mounting a semiconductor device, due to the pressure difference between the inside and outside of the sheet 11, a contact force equal to the value obtained by multiplying the narrow area of either the semiconductor chip 2 or the back surface area of the substrate 4 by the pressure difference is generated between the electrodes 1 and each other. Acts between 3. Since the area of the back surface of the semiconductor chip 2 or the substrate 4 is generally much larger than the total area of the contact surfaces of the plurality of electrodes, the contact pressure between the electrodes is much larger than the pressure difference between the inside and outside of the sheet.
第１図はこの発明の実施例を示す断面図であり、第２図
は第１図のものを生産する工程の一段階を示す断面図で
ある。FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing one stage of the process of producing the device shown in FIG.
これらの図面を参照して説明すると、バンブ電極１を持
った半導体チップ２とこのバンブ電極１に対向する位置
に設けられた基板４の基板電極３とを接触させ、可撓性
のあるシート１１で取り囲んで包む。シート１１はシー
ト内部を真空にするための配管用の吸気孔１２と基板４
に取付けた電気配線のり一ド１３を引出すためのリード
孔１４とを持っている。このリード孔１４にリード１３
を引出して加熱触着し、気密性を確保する。この状態で
吸気孔１２からシート１１の内部の空気を吸引除去する
と大気圧によりシート１１が押しつぶされ、シート１１
内の半導体チップ２のバンブ電極１と基板４の基板電極
３とが圧着して接続される。その後に吸気孔１２を封止
して実装が完了し、第１図に示す半導体装置が得られる
。電極相互の接触力は半導体チップ２又は基板４の背面
の面積のうちいずれか一方の狭い方の面積に大気圧を乗
じたものをバンブ電極１の数で割ったものになる。接触
圧は前記接触力を電極相互の接触面積で割ったものにな
る。To explain with reference to these drawings, a semiconductor chip 2 having a bump electrode 1 is brought into contact with a substrate electrode 3 of a substrate 4 provided at a position facing the bump electrode 1, and a flexible sheet 11 is Surround and wrap. The sheet 11 has an intake hole 12 for piping and a substrate 4 to create a vacuum inside the sheet.
It has a lead hole 14 for pulling out the electrical wiring glue 13 attached to the holder. Lead 13 is inserted into this lead hole 14.
Pull it out and heat it to ensure airtightness. In this state, when the air inside the sheet 11 is removed by suction from the intake hole 12, the sheet 11 is crushed by atmospheric pressure, and the sheet 11 is
The bump electrode 1 of the semiconductor chip 2 and the substrate electrode 3 of the substrate 4 are connected by pressure bonding. Thereafter, the air intake hole 12 is sealed to complete the mounting, and the semiconductor device shown in FIG. 1 is obtained. The contact force between the electrodes is equal to the product of the smaller area of either the semiconductor chip 2 or the back surface of the substrate 4 multiplied by the atmospheric pressure divided by the number of bump electrodes 1. The contact pressure is the contact force divided by the contact area between the electrodes.
前記の実施例において、基板４側にバンブ電極を設けて
もよいことは当然である。また真空らしきの時にはシー
ト１１の内部にある半導体チップ２と基板４との相対位
置をシート１１の外部から調整することができる。これ
に対し両者の対向面に位置決めのための凹凸を設けても
よい。この凹凸は対向面と直角方向には寸法上の遊びを
設けて電極相互の接触を妨げないようにする。リード孔
１４を設けないで吸気孔１２からリード１３を引出し、
吸気孔１２に接続する図示しない配管の中を通しもよい
。リード１３が導体と被覆を持つものでは導体と被覆と
の間の気密処理が必要であり、導体がより線である時に
はより線の間の隙間から空気が侵入しないような特別な
工夫が必要である。In the embodiments described above, it goes without saying that a bump electrode may be provided on the substrate 4 side. Further, when a vacuum is applied, the relative position between the semiconductor chip 2 and the substrate 4 inside the sheet 11 can be adjusted from outside the sheet 11. On the other hand, unevenness for positioning may be provided on the opposing surfaces of the two. The unevenness provides dimensional play in the direction perpendicular to the facing surface so as not to prevent contact between the electrodes. The lead 13 is pulled out from the intake hole 12 without providing the lead hole 14,
It may also be passed through a pipe (not shown) connected to the intake hole 12. If the lead 13 has a conductor and a sheath, airtight treatment is required between the conductor and sheath, and when the conductor is a stranded wire, special measures must be taken to prevent air from entering through the gaps between the strands. be.
リードについてのこれらの処理技術についてここでは詳
述しないが公知の方法が多数確立している、シート１１
をチューブ状にして両端を吸気孔とすることもできる。These processing techniques for leads are not described in detail here, but many known methods have been established.
It is also possible to make it into a tube and have air intake holes at both ends.
図示しないが、上下２枚の可撓性のシートで半導体チッ
プと基板とを包み、真空中でシートの全周を封止し、そ
の後に大気中に取り出す方法によってもこの発明の半導
体装置は得られる。Although not shown, the semiconductor device of the present invention can also be obtained by wrapping a semiconductor chip and a substrate in two flexible sheets (upper and lower), sealing the entire circumference of the sheet in a vacuum, and then taking it out into the atmosphere. It will be done.
この発明によればシートの内外の圧力差で半導体チップ
と基板との相互の電極が接触するので、半導体チップと
基板とに材料の熱膨張係数の差があっても接続部に歪み
や断線の恐れがないという効果があり、加熱そのものが
無いので加熱温度管理から全く自由になり、シートが粉
塵や湿気に対し半導体装置を保護するという効果がある
。According to this invention, the electrodes of the semiconductor chip and the substrate come into contact with each other due to the pressure difference between the inside and outside of the sheet, so even if there is a difference in the coefficient of thermal expansion of the materials between the semiconductor chip and the substrate, there will be no distortion or disconnection at the connection part. There is an effect that there is no fear, and since there is no heating itself, there is complete freedom from heating temperature control, and the sheet protects the semiconductor device from dust and moisture.
第１図はこの発明の実施例を示す断面図であり、第２図
は第１図のものを生産する工程の一段階を示す断面図で
あり、第３図は従来の技術による半導体装置を示す断面
図であり、第４図は第３図のものを生産する工程の一段
階を示す断面図である。
１・・・バンプ電極、３・・・基板電極、５・・・合金
Ｎ。
第１図
第３図FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view showing one step in the process of producing the device shown in FIG. 1, and FIG. FIG. 4 is a cross-sectional view showing one step in the process of producing the product shown in FIG. 3. DESCRIPTION OF SYMBOLS 1... Bump electrode, 3... Substrate electrode, 5... Alloy N. Figure 1 Figure 3
Claims (1)
うに対向させて可撓性のシートで気密に包み、このシー
トに設けた吸気口を介して前記シートの内部を真空にし
て前記相互の電極を圧接することを特徴とする半導体装
置の実装方法。(1) A semiconductor chip and a substrate are placed facing each other so that their electrodes are in contact with each other, and are airtightly wrapped in a flexible sheet, and the interior of the sheet is evacuated through an air inlet provided in the sheet. 1. A method for mounting a semiconductor device, comprising press-welding electrodes of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63140868A JPH01309343A (en) | 1988-06-08 | 1988-06-08 | Mounting of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63140868A JPH01309343A (en) | 1988-06-08 | 1988-06-08 | Mounting of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01309343A true JPH01309343A (en) | 1989-12-13 |
Family
ID=15278616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63140868A Pending JPH01309343A (en) | 1988-06-08 | 1988-06-08 | Mounting of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01309343A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5352629A (en) * | 1993-01-19 | 1994-10-04 | General Electric Company | Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules |
| EP1280196A1 (en) * | 2001-07-18 | 2003-01-29 | Abb Research Ltd. | Process for bonding electronic devices to substrates |
| US6513236B2 (en) | 2000-02-18 | 2003-02-04 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing bump-component mounted body and device for manufacturing the same |
| EP1310990A1 (en) * | 2001-11-09 | 2003-05-14 | Abb Research Ltd. | Bonding method with improved alignment |
-
1988
- 1988-06-08 JP JP63140868A patent/JPH01309343A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5352629A (en) * | 1993-01-19 | 1994-10-04 | General Electric Company | Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules |
| US6513236B2 (en) | 2000-02-18 | 2003-02-04 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing bump-component mounted body and device for manufacturing the same |
| EP1139410A3 (en) * | 2000-02-18 | 2003-09-24 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing bump-component mounted body and device for manufacturing the same |
| EP1280196A1 (en) * | 2001-07-18 | 2003-01-29 | Abb Research Ltd. | Process for bonding electronic devices to substrates |
| US6935556B2 (en) | 2001-07-18 | 2005-08-30 | Abb Research Ltd. | Method for mounting electronic components on substrates |
| EP1310990A1 (en) * | 2001-11-09 | 2003-05-14 | Abb Research Ltd. | Bonding method with improved alignment |
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