JPH01308076A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To raise integration and to enhance a current driving capacity by forming a drain at the center of a semiconductor, an offset at its periphery and a trench at its periphery, and forming an insulated gate in the trench. CONSTITUTION:A drain 14 is formed in a semiconductor layer on an insulator, an insulated gate 16 is provided around it through an offset 15, and a source 13 is formed at its outside. Here, a trench 17 is formed in depth to the intermediate of the thickness of the layer in the region surrounding the offset 15, and the gate 16 is formed therein. An island of a recrystallized semiconductor layer is formed on the insulator, a drain 14 of high concentration is formed at the center of the island, the offset 15 of relatively low concentration is formed around the drain, the source 13 of high concentration is formed further at the outside, the trench 17 is formed by partly etching the island of the layer inside the source 13 around the offset 15, and the gate 16 may be formed therein.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device including an offset-type FET, the offset-type FETf! has a high degree of integration and a high current drive capability. : Aiming at providing aging semiconductor devices, a drain region is formed in the center of a semiconductor layer on an insulator (SOI) region, and an insulator 1 structure is formed surrounding the drain region via an offset region. A semiconductor device including an offset type FET in which a source region is formed on the outside of the offset type FET, wherein a trench is formed in a region surrounding the offset region of the semiconductor layer to a depth up to the middle of the thickness of the semiconductor layer, and a trench is formed within the trench. The structure is such that an insulated gate structure is formed.

[Industrial Application Field] The present invention relates to a semiconductor device formed on a semiconductor on an insulator (SOI), and particularly to a semiconductor device using an offset type FET.

In recent years, in the field of power ICs, it has become necessary to develop elements with high breakdown voltages. It is also desirable that the on-resistance be low.

[Prior Art] A conventional offset type ring gate FET element is shown in FIGS. ,
The offset region 35 and the insulated gate structure 36 are arranged concentrically.

The insulating substrate 31 is composed of, for example, a silicon substrate covered with a silicon oxide film. The semiconductor layer island 32 is made of high resistivity p (or i) type silicon, for example, and is formed by recrystallizing a polycrystalline or amorphous silicon island.

The drain region 34 for extracting carriers is formed of a highly doped n+ type region in the center of the island, and around it is a relatively lightly doped n-type region that offsets the drain region 34 from the insulated gate structure 36 to increase the withstand voltage. The area is placed
This constitutes an offset region 35. A high concentration rl'' type region is formed in the outer periphery of the island, and a gate electrode is provided via an insulating film on a plane region in the middle between the six source regions 33 and the offset region 35 that constitute the source region 33. and constitutes an insulated gate structure 36.

[Problems to be Solved by the Invention] According to the offset type FET shown in FIGS. 3(A) and 3(B), since the gate is arranged two-dimensionally, it is difficult to increase the degree of integration, and the current drive capacity ( drivability
) cannot be said to be high enough.

An object of the present invention is to provide a semiconductor device including an offset type FET with an increased degree of integration and a high current drive capability.

Another object of the present invention is to provide a method for manufacturing a semiconductor device including an offset FET with an increased degree of integration and a high current drive capability.

[Means for solving the problem] A drain region is placed in the center of a semiconductor-on-insulator (SOI) region, an offset region is arranged around it, a trench is formed around it, and an insulated gate structure is formed within the trench. be done.

The gate structure surrounds the drain region and the offset region three-dimensionally.

A drain region is formed in the center of the SO2 region, and an offset region is formed around it. After forming a source region further outside, a trench is formed surrounding the offset region, and an insulated gate structure is formed within the trench.

[Operation] In the present invention, the gate structure is formed in a trench formed from the surface of the semiconductor layer to the inside, forming a three-dimensional structure, so that the channel length can be increased and the degree of integration can be increased.

Furthermore, the three-dimensional insulated gate structure three-dimensionally surrounds the drain region and the offset region, so that the cross-sectional area of the current path can be increased, and the current driving capability can be increased.

[Embodiment] FIGS. 1A and 1B show a semiconductor device including an offset type FET according to an embodiment of the present invention.

(A> is a sectional view, and (B) is a perspective view.

A semiconductor N12 made of silicon, for example, is formed on the insulating substrate 11 to form a Sol structure. The insulating substrate 11 is composed of, for example, a silicon substrate covered with a silicon oxide film. The semiconductor layer 12 is, for example, a P-type or l-type high resistivity region. An n+ type (high concentration, low resistivity) drain region 14 is located at the center of the surface of the semiconductor layer 12.
is formed, and an n-type relatively low concentration (high resistivity) offset region 15 is formed surrounding it. Offset I - Trench in contact with the outside of the head area 15
17 are formed. The surface of the trench is covered with an insulating film 18, on which, for example, one layer of doped polycrystalline silicon with low resistivity is deposited to make the surface substantially flush with the outside of the trench. The insulating film 18 and one polycrystalline silicon constitute the insulated gate structure 16. A highly doped (low resistivity) n-type source region 13 is formed surrounding the outside of the trench 17 . drain region 14, offset region 15,
Trench 17, insulated gate structure 16, and source region 13 are arranged concentrically. In addition to concentric circles, the shape may be an ellipse, a rectangle with radiused corners, or the like.

The path of electrons from the source region 13 to the drain region 14 is blocked by the ρ wall region in the trench portion. When a positive voltage is applied to the polycrystalline silicon 19 serving as the gate electrode and an n-type channel is induced on the semiconductor surface of the trench portion, a current path is formed along the side and bottom surfaces of the trench.

Compared to a conventional planar structure, the channel length increases as it goes up and down along the sides of the trench.

The inner side surface of the almost vertical trench has a drain region 14 and an offset region 15 formed almost entirely in the surface region.
It is configured to face the Compared to prior art structures in which insulated gate structures are formed in the same plane, a gate structure that penetrates into the semiconductor can form a current path with a large cross-sectional area. The electric field distribution from the channel inside the trench 17 to the drain region 14 changes, and the offset resistance can also be lowered.

Next, an example of a manufacturing process for a semiconductor device including an offset type FET according to an embodiment of the present invention will be described with reference to FIGS. 2(A) to 2(D).

Referring to FIG. 2(A), approximately 2 μrn #1 silicon II! 21 is formed, and an impurity-free polycrystalline silicon film 22 is deposited thereon to a thickness of about 1 μm, for example, by low pressure (LP) CVD. The polycrystalline wA22 is recrystallized by scanning with an Ar laser beam or the like. Insulated substrate 20fJ if necessary! Ion implantation is performed on the I surface to prevent back channels, and patterning is performed to create an SOI structure.

After the SOI topography is formed, impurity doping for forming an offset region is performed over the entire surface by, for example, phosphorus ion implantation to form an n-layer 23 having a depth of about 0608 μm.

Next, as shown in FIG. 2(B), the portion that will become the offset region is covered with photoresist l-24, and high-4 ion implantation of, for example, phosphorus is performed for the source and drain regions.
Source region 13 and drain region 1 with a depth of about 0.17m
Get 4.

Thereafter, as shown in FIG. 2(C), the insulated gate structure 16 is
Trench etching is performed using anisotropic reactive ion etching in the area where the trench is to be formed, thereby forming an annular trench 17 with a roughly rectangular cross section and a depth of about 0.7 μm.

The remaining n- area becomes the offset area 15. On the surface of the trench 17, a silicon oxide film, which will become the gate insulating film 18, is formed in a thickness of, for example, 1,000 to 2,000 layers.

Thereafter, as shown in FIG. 2(D), the trench 17 is filled with one doped polycrystalline silicon, and a source electrode, a gate electrode, and a drain electrode are appropriately drawn out from the surface by evaporation of 11fiAI or the like.

Thereafter, the semiconductor device is manufactured using a process for manufacturing a normal offset type FET.

For ion implantation of the Ω- layer, for example, P+ ions are accelerated at an energy of 60 KeV and at a dose of (2 to 3) x 1012.
/12, the gate oxide film thickness is 1000 to 2000, the offset length is 1 to 100 μm, and the breakdown voltage is 200 μm.
It is 20 to 30 μm for a V device.

[Effects of the Invention] According to the present invention, the degree of integration of offset type FETs can be increased,
Current drive capability can also be increased.

This will greatly contribute to the field of power IC applications.

[Brief explanation of the drawing]

1A and 1B are cross-sectional views and perspective views of a semiconductor device including an offset FET according to an embodiment of the present invention, and FIGS. 2A to 2D are manufacturing processes according to an embodiment of the present invention. 3(A) and 3(B) are a plan view and a sectional view of a conventional offset-type FET. In the figure, 13 source region 14 drain region 15 offset region 16 insulated gate structure 17 trench 18 gate insulating film 19 polycrystalline silicon 21 insulator 22 semiconductor layer island Q-ku mountain

Claims (2)

[Claims] (1) A drain region (14) is formed in a region of a semiconductor layer on an insulator (SOI), an insulated gate structure (16) is provided surrounding the drain region via an offset region (15), and an insulated gate structure (16) is provided outside the drain region. A semiconductor device including an offset type FET in which a source region (13) is formed, wherein a trench (17) is formed in a region surrounding the offset region (15) of the semiconductor layer to a depth up to the middle of the semiconductor layer thickness; A semiconductor device including an offset type FET, characterized in that an insulated gate structure (16) is formed within a trench (17). (2) A drain region (14) is formed in a region of a semiconductor layer on an insulator (SOI), an insulated gate structure (16) is provided surrounding the drain region via an offset region (15), and an insulated gate structure (16) is provided outside the drain region. A method of manufacturing a semiconductor device including an offset FET with a source region (13) formed therein, the method comprising: an island (22) of a recrystallized semiconductor layer on an insulator (21);
A highly doped drain region (14) is formed in the center of the island, and a relatively lightly doped offset region (14) surrounds the drain region.
5), a highly concentrated source region (13) is formed further outside, and a source region (13) is formed surrounding the offset region (15).
selectively etching the island (22) of the semiconductor layer in an inner part of the semiconductor layer to form a trench (17), and forming an insulated gate structure (16) within the trench (17); A method for manufacturing a semiconductor device including a featured offset type FET.